A study of the applicability of hopfield decision neural nets to VLSI CAD
DAC '89 Proceedings of the 26th ACM/IEEE Design Automation Conference
VLSI cell placement techniques
ACM Computing Surveys (CSUR)
Near-optimal placement using a quadratic objective function
DAC '85 Proceedings of the 22nd ACM/IEEE Design Automation Conference
The integration of an advanced gate array router into a fully automated design system
DAC '85 Proceedings of the 22nd ACM/IEEE Design Automation Conference
Automatic placement a review of current techniques (tutorial session)
DAC '86 Proceedings of the 23rd ACM/IEEE Design Automation Conference
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It is known [1] that the optimal placement of devices on a carrier is NP-complete. So algorithms are forced to rely on heuristics in order to generate placements which are of high quality even if not globally optimal. This paper proposes the use of a metric which is the sum of the squares of the lengths of connections, for which a globally optimal assignment can be derived when overlapping components are ignored. A second placement phase maps this into a non-overlapping placement on the carrier while perturbing the derived placement as little as possible. This is essentially the metric used in [4] although not explicitly stated. However, [4] does not deal with the problems of fixed devices, IO's and other constraints which are important to VLSI design. The current paper seeks to incorporate these constraints into the model from the beginning.