Near-optimal placement using a quadratic objective function
DAC '85 Proceedings of the 22nd ACM/IEEE Design Automation Conference
Efficient placement and routing techniques for master slice LSI
DAC '80 Proceedings of the 17th Design Automation Conference
Some experimental results on placement techniques
DAC '76 Proceedings of the 13th Design Automation Conference
A linear-time heuristic for improving network partitions
DAC '82 Proceedings of the 19th Design Automation Conference
DAC '89 Proceedings of the 26th ACM/IEEE Design Automation Conference
Using controlled experiments in layout
ACM SIGDA Newsletter
Proceedings of the 1997 international symposium on Physical design
Proceedings of the conference on Design, automation and test in Europe
An efficient heuristic for standard-cell placement
Integration, the VLSI Journal
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This paper describes a study of placement procedures for VLSI Standard Cell Layout. The procedures studied are Simulated Annealing, Min Cut placement, and a number of improvements to Min Cut placement including a technique called Terminal Propagation which allows Min Cut to include the effect of connections to external cells. The Min Cut procedures are coupled with a Force Directed Pairwise Interchange (FDPI) algorithm for placement improvement. For the same problem these techniques produce a range of solutions with a typical standard deviation 4% for the total wire length and 3% to 4% for the routed area. The spread of results for Simulated Annealing is even larger. This distribution of results for a given algorithm implies that mean results of many placements should be used when comparing algorithms. We find that the Min Cut partitioning with simplified Terminal Propagation is the most efficient placement procedure studied.