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ICCAD '94 Proceedings of the 1994 IEEE/ACM international conference on Computer-aided design
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DAC '94 Proceedings of the 31st annual Design Automation Conference
ICCAD '95 Proceedings of the 1995 IEEE/ACM international conference on Computer-aided design
A method for generating random circuits and its application to routability measurement
Proceedings of the 1996 ACM fourth international symposium on Field-programmable gate arrays
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DAC '96 Proceedings of the 33rd annual Design Automation Conference
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ICCAD '93 Proceedings of the 1993 IEEE/ACM international conference on Computer-aided design
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DAC '86 Proceedings of the 23rd ACM/IEEE Design Automation Conference
A Technique for Drawing Directed Graphs
IEEE Transactions on Software Engineering
VIS: A System for Verification and Synthesis
CAV '96 Proceedings of the 8th International Conference on Computer Aided Verification
Design of experiments in BDD variable ordering: lessons learned
Proceedings of the 1998 IEEE/ACM international conference on Computer-aided design
Towards synthetic benchmark circuits for evaluating timing-driven CAD tools
ISPD '99 Proceedings of the 1999 international symposium on Physical design
Generation of very large circuits to benchmark the partitioning of FPGA
ISPD '99 Proceedings of the 1999 international symposium on Physical design
Regression-based RTL power models for controllers
GLSVLSI '00 Proceedings of the 10th Great Lakes symposium on VLSI
Design of Experiments for Evaluation of BDD Packages Using Controlled Circuit Mutations
FMCAD '98 Proceedings of the Second International Conference on Formal Methods in Computer-Aided Design
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ALENEX '99 Selected papers from the International Workshop on Algorithm Engineering and Experimentation
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ALENEX '99 Selected papers from the International Workshop on Algorithm Engineering and Experimentation
Heuristics, Experimental Subjects, and Treatment Evaluation in Bigraph Crossing Minimization
Journal of Experimental Algorithmics (JEA)
Perturb+mutate: Semisynthetic circuit generation for incremental placement and routing
ACM Transactions on Reconfigurable Technology and Systems (TRETS)
Hierarchical Benchmark Circuit Generation for FPGA Architecture Evaluation
ACM Transactions on Embedded Computing Systems (TECS) - Special Section on CAPA'09, Special Section on WHS'09, and Special Section VCPSS' 09
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This paper formalizes the synthesis process of wiring signature-invariant (WSI) combinational circuit mutants. The signature \sigma_0 is defined by a reference circuit \eta_0, which itself is modeled as a canonical form of a directed bipartite graph. A wiring perturbation \gamma induces a perturbed reference circuit \eta_{\gamma}. A number of mutant circuits \eta_{\gamma_i} can be resynthesized from the perturbed circuit \eta_\gamma. The mutants of interest are the ones that belong to the wiring-signature-invariant equivalence class {\cal N}_\sigma{}_0, i.e. the mutants \eta_{\gamma{}_i} \in {\cal N}_\sigma{}_0. Circuit mutants \eta_{\gamma{}_i} \in {\cal N}_\sigma{}_0 have a number of useful properties. For any wiring perturbation \gamma, the size of the wiring-signature-invariant equivalence class is huge. Notably, circuits in this class are not random, although for unbiased testing and benchmarking purposes, mutant selections from this class are typically random. For each reference circuit, we synthesized eight equivalence subclasses of circuit mutants, based on 0 to 100\% perturbation. Each subclass contains 100 randomly chosen mutant circuits, each listed in a different random order. The 14,400 benchmarking experiments with 3200 mutants in 4 equivalence classes, covering 13 typical EDA algorithms, demonstrate that an unbiased random selection of such circuits can lead to statistically meaningful differentiation and improvements of existing and new algorithms.