Random generation of test instances for logic optimizers

Authors:
Kazuo Iwama;Kensuke Hino
Affiliations:
Department of Computer Science and Communication Engineering, Kyushu University, Hakozaki, Fukuoka 812, Japan;Department of Computer Science and Communication Engineering, Kyushu University, Hakozaki, Fukuoka 812, Japan
Venue:
DAC '94 Proceedings of the 31st annual Design Automation Conference
Year:
1994

Citing 2
Cited 7

The Transduction Method-Design of Logic Networks Based on Permissible Functions

IEEE Transactions on Computers
Random Generation of Satisfiable and Unsatisfiable CNF Predicates

Proceedings of the IFIP 12th World Computer Congress on Algorithms, Software, Architecture - Information Processing '92, Volume 1 - Volume I

Synthesis of wiring signature-invariant equivalence class circuit mutants and applications to benchmarking

Proceedings of the conference on Design, automation and test in Europe
Effective use of boolean satisfiability procedures in the formal verification of superscalar and VLIW

Proceedings of the 38th annual Design Automation Conference
Verifying the correctness of FPGA logic synthesis algorithms

FPGA '03 Proceedings of the 2003 ACM/SIGDA eleventh international symposium on Field programmable gate arrays
Effective use of boolean satisfiability procedures in the formal verification of superscalar and VLIW microprocessors

Journal of Symbolic Computation
Random Benchmark Circuits with Controlled Attributes

EDTC '97 Proceedings of the 1997 European conference on Design and Test
Optimality and scalability study of existing placement algorithms

ASP-DAC '03 Proceedings of the 2003 Asia and South Pacific Design Automation Conference
Performance test of local search algorithms using new types of random CNF formulas

IJCAI'95 Proceedings of the 14th international joint conference on Artificial intelligence - Volume 1

Quantified Score

Hi-index	0.00

Visualization

Abstract