PRO - an automatic string placement program for polycell layout
DAC '76 Proceedings of the 13th Design Automation Conference
DAC '76 Proceedings of the 13th Design Automation Conference
A proper model for the partitioning of electrical circuits
DAC '72 Proceedings of the 9th Design Automation Workshop
Wire routing by optimizing channel assignment within large apertures
DAC '71 Proceedings of the 8th Design Automation Workshop
The chip layout problem: A placement procedure for lsi
DAC '77 Proceedings of the 14th Design Automation Conference
The chip layout problem: An automatic wiring procedure
DAC '77 Proceedings of the 14th Design Automation Conference
The minimum width routing of A 2-row 2-layer polycell-layout
DAC '79 Proceedings of the 16th Design Automation Conference
A placement capability based on partitioning
DAC '79 Proceedings of the 16th Design Automation Conference
Constructing test cases for partitioning heuristics
IEEE Transactions on Computers
A linear-time heuristic for improving network partitions
25 years of DAC Papers on Twenty-five years of electronic design automation
Global wiring on a wire routing machine
25 years of DAC Papers on Twenty-five years of electronic design automation
A new placement level wirability estimate with measurements
ACM SIGDA Newsletter
VLSI cell placement techniques
ACM Computing Surveys (CSUR)
A new min-cut placement algorithm for timing assurance layout design meeting net length constraint
DAC '90 Proceedings of the 27th ACM/IEEE Design Automation Conference
Adaptive cut line selection in min-cut placement for large scale sea-of-gates arrays
ICCAD '94 Proceedings of the 1994 IEEE/ACM international conference on Computer-aided design
Analysis of placement procedures for VLSI standard cell layout
DAC '86 Proceedings of the 23rd ACM/IEEE Design Automation Conference
An over-cell gate array channel router
DAC '83 Proceedings of the 20th Design Automation Conference
Design automation status in Japan
DAC '81 Proceedings of the 18th Design Automation Conference
A linear-time heuristic for improving network partitions
DAC '82 Proceedings of the 19th Design Automation Conference
Global wiring on a wire routing machine
DAC '82 Proceedings of the 19th Design Automation Conference
A behavioral synthesis system for asynchronous circuits
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
An Improved Min-Cut Algonthm for Partitioning VLSI Networks
IEEE Transactions on Computers
Number of vias: a control parameter for global wiring of high-density chips
IBM Journal of Research and Development
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This paper deals with placement and routing techniques for master slice LSIs. The basic idea of both techniques is to make wiring density on the chip more uniform. Algorithms and some experimental results are described.