Genetic packing of rectangles on transputers
Proceedings of the world transputer user group (WOTUG) conference on Transputing '91
Macro-cell and module placement by genetic adaptive search with bitmap-represented chromosome
Integration, the VLSI Journal
DAC '97 Proceedings of the 34th annual Design Automation Conference
Generic global placement and floorplanning
DAC '98 Proceedings of the 35th annual Design Automation Conference
Genetic algorithms for VLSI design, layout & test automation
Genetic algorithms for VLSI design, layout & test automation
A new algorithm for floorplan design
DAC '86 Proceedings of the 23rd ACM/IEEE Design Automation Conference
Layout tools for analog ICs and mixed-signal SoCs: a survey
ISPD '00 Proceedings of the 2000 international symposium on Physical design
Timing-driven placement based on partitioning with dynamic cut-net control
Proceedings of the 37th Annual Design Automation Conference
A GA with heuristic-based decoder for IC floorplanning
Integration, the VLSI Journal
A common mode feedback structure for differential OpAmps using NMOS depletion transistors
Analog Integrated Circuits and Signal Processing
Analog Device-Level Layout Automation
Analog Device-Level Layout Automation
VISI Physical Design Automation: Theory and Practice
VISI Physical Design Automation: Theory and Practice
Chip design: automation comes to analog
IEEE Spectrum - IEEE medal of honor Herwig Kogelnik
Dragon2000: standard-cell placement tool for large industry circuits
Proceedings of the 2000 IEEE/ACM international conference on Computer-aided design
A Novel Analog Module Generator Environment
EDTC '96 Proceedings of the 1996 European conference on Design and Test
Hybrid genetic algorithms for constrained placement problems
IEEE Transactions on Evolutionary Computation
Causally-guided evolutionary optimization and its application to antenna array design
Integrated Computer-Aided Engineering
A computational intelligence optimization algorithm: Cloud drops algorithm
Integrated Computer-Aided Engineering
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Practical analog layout synthesis techniques have been the subject of active research for the past two decades to address the growing gap between the increasing chip functionality and the design productivity. In this paper, we present a novel macro-cell placement approach following the optimization flow of a genetic algorithm controlled by the methodology of simulated annealing. A process of cell slide is adopted to drastically reduce the configuration space without degrading search opportunities. In addition, this cell-slide process is used to satisfy the symmetry constraints essential for analog layouts. Furthermore, the dedicated cost function captures subtle electrical and geometrical constraints, such as area, net length, aspect ratio, proximity, parasitic effects, etc. required for analog layout and subsequent intellectual property reuse. To study the algorithm parameters, fractional factorial experiments and a meta-GA approach are employed. The proposed algorithm has been tested using several analog circuits. Compared to the simulated-annealing approach, the dominant one currently used for the analog placement problem, the proposed algorithm requires less computation time while generating higher quality layouts, comparable to expert manual placements. Furthermore, our hybrid algorithm and the method of parameter optimization can be readily adapted to different optimization problems across disciplines.