The ISPD98 circuit benchmark suite
ISPD '98 Proceedings of the 1998 international symposium on Physical design
Multilevel hypergraph partitioning: applications in VLSI domain
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
System-level performance evaluation of three-dimensional integrated circuits
IEEE Transactions on Very Large Scale Integration (VLSI) Systems - Special issue on system-level interconnect prediction
Impact of three-dimensional architectures on interconnects in gigascale integration
IEEE Transactions on Very Large Scale Integration (VLSI) Systems - System Level Design
Stochastic wire-length and delay distributions of 3-dimensional circuits
Proceedings of the 2000 IEEE/ACM international conference on Computer-aided design
An efficient and effective detailed placement algorithm
ICCAD '05 Proceedings of the 2005 IEEE/ACM International conference on Computer-aided design
Placement of 3D ICs with thermal and interlayer via considerations
Proceedings of the 44th annual Design Automation Conference
Thermal-Aware 3D IC Placement Via Transformation
ASP-DAC '07 Proceedings of the 2007 Asia and South Pacific Design Automation Conference
A multilevel analytical placement for 3D ICs
Proceedings of the 2009 Asia and South Pacific Design Automation Conference
Physical design implementation for 3D IC: methodology and tools
Proceedings of the 19th international symposium on Physical design
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To sustain the pace of integration density improvement, 3-D IC technology is hailed as a "Beyond Moore" driver. It has been demonstrated to have great potential to diminish footprint, reduce interconnect delay, promote system performance, decrease power consumption and facilitate integration of heterogeneous processes. Besides, it is commonly cited as a means of reducing lateral wirelength. Some early theoretical and experimental studies have also shown that 3-D IC can significantly reduce lateral wirelength. However, the effect of through-silicon via (TSV) area overhead on the wirelength has been largely overlooked. In this paper, we derive a mathematical upper bound on the wirelength benefit of placing a circuit in 3-D that takes the TSV area overhead into account. For a set of IBM placement benchmarks scaled to the 32 nm process, we showthat 3-D integration cannot help to reduce the wirelength under current TSV technologies.