Stochastic wire-length and delay distributions of 3-dimensional circuits

Authors:
Rongtian Zhang;Kaushik Roy;Cheng Kok Koh;David B. Janes
Affiliations:
ECE, Purdue University, West Lafayette, IN;ECE, Purdue University, West Lafayette, IN;ECE, Purdue University, West Lafayette, IN;ECE, Purdue University, West Lafayette, IN
Venue:
Proceedings of the 2000 IEEE/ACM international conference on Computer-aided design
Year:
2000

Citing 2
Cited 9

Wire segmenting for improved buffer insertion

DAC '97 Proceedings of the 34th annual Design Automation Conference
Three dimensional metallization for vertically integrated circuits

Microelectronic Engineering

Wirelength estimation based on rent exponents of partitioning and placement

Proceedings of the 2001 international workshop on System-level interconnect prediction
Exploring SOI device structures and interconnect architecures for 3-dimensional integration

Proceedings of the 38th annual Design Automation Conference
Vertically integrated SOI circuits for low-power and high-performance applications

IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Power Trends and Performance Characterization of 3-Dimensional Integration for Future Technology Generations

ISQED '01 Proceedings of the 2nd International Symposium on Quality Electronic Design
A 3-D FPGA wire resource prediction model validated using a 3-D placement and routing tool

Proceedings of the 2005 international workshop on System level interconnect prediction
Through-silicon-via aware interconnect prediction and optimization for 3D stacked ICs

Proceedings of the 11th international workshop on System level interconnect prediction
Through-silicon-via-aware delay and power prediction model for buffered interconnects in 3D ICs

Proceedings of the 12th ACM/IEEE international workshop on System level interconnect prediction
Power consumption and performance analysis of 3D NoCs

ACSAC'07 Proceedings of the 12th Asia-Pacific conference on Advances in Computer Systems Architecture
Rethinking the wirelength benefit of 3-D integration

IEEE Transactions on Very Large Scale Integration (VLSI) Systems

Quantified Score

Hi-index	0.00

Visualization

Abstract

3-D technology promises higher integration density and lower interconnection complexity and delay. At present, however, not much work on circuit applications has been done due to lack of insight into 3-D circuit architecture and performance. In this paper, we investigate the interconnect distributions of 3-D circuits. We divide the 3-D interconnects into horizontal wires and vertical wires and derive their wire-length distributions, respectively. Based on the stochastic wire-length distributions, we calculate 3-D circuit interconnect delay distribution. We show that 3-D structures effectively reduce the number of long delay nets, significantly reduce the number of repeaters needed, and dramatically improve the performance. With 3-D structures, a circuit can work at a much higher clock rate (double, even triple) than with 2-D. However, we also show that the impacts of vertical wires on chip area and interconnect delay may limit the number of device layers that we can integrate.