Multilevel hypergraph partitioning: application in VLSI domain
DAC '97 Proceedings of the 34th annual Design Automation Conference
The ISPD98 circuit benchmark suite
ISPD '98 Proceedings of the 1998 international symposium on Physical design
Performance analysis and technology of 3-D ICs
SLIP '00 Proceedings of the 2000 international workshop on System-level interconnect prediction
Prediction of interconnect fan-out distribution using Rent's rule
SLIP '00 Proceedings of the 2000 international workshop on System-level interconnect prediction
Managing interconnect resources (tutorial)
SLIP '00 Proceedings of the 2000 international workshop on System-level interconnect prediction
Can recursive bisection alone produce routable placements?
Proceedings of the 37th Annual Design Automation Conference
Global objectives for standard cell placement
GLSVLSI '01 Proceedings of the 11th Great Lakes symposium on VLSI
Congestion estimation during top-down placement
Proceedings of the 2001 international symposium on Physical design
Stochastic wire-length and delay distributions of 3-dimensional circuits
Proceedings of the 2000 IEEE/ACM international conference on Computer-aided design
Dragon2000: standard-cell placement tool for large industry circuits
Proceedings of the 2000 IEEE/ACM international conference on Computer-aided design
GLS '99 Proceedings of the Ninth Great Lakes Symposium on VLSI
Congestion estimation during top-down placement
Proceedings of the 2001 international symposium on Physical design
Placement rent exponent calculation methods, temporal behaviour and FPGA architecture evaluation
Proceedings of the 2003 international workshop on System-level interconnect prediction
Calibration of rent's rule models for three-dimensional integrated circuits
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Unifying mesh- and tree-based programmable interconnect
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Assessment of on-chip wire-length distribution models
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Predicting interconnect requirements in ultra-large-scale integrated control logic circuitry
Proceedings of the 2005 international workshop on System level interconnect prediction
Intrinsic shortest path length: a new, accurate a priori wirelength estimator
ICCAD '05 Proceedings of the 2005 IEEE/ACM International conference on Computer-aided design
Tutorial on congestion prediction
Proceedings of the 2007 international workshop on System level interconnect prediction
Using circuit structural analysis techniques for networks in systems biology
Proceedings of the 11th international workshop on System level interconnect prediction
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Rent's rule based FPGA packing for routability optimization
Proceedings of the 2014 ACM/SIGDA international symposium on Field-programmable gate arrays
Hi-index | 0.00 |
Wirelength estimation is one of the most important Rent's rule applications. Traditional Rent exponent extraction is based on recursive bipartitioning. However, the obtained exponent may not be appropriate for wirelength estimation. In this paper, we propose the concepts of partitioning-based Rent exponent and placement-based Rent exponent. The relationship between them is analyzed and empirically verified. Experiments on large circuits show that for wirelength estimation, the Rent exponent extracted from placement is more reasonable than that from partitioning.