Proceedings of the 36th annual ACM/IEEE Design Automation Conference
The interpretation and application of Rent's rule
IEEE Transactions on Very Large Scale Integration (VLSI) Systems - Special issue on system-level interconnect prediction
Wirelength estimation based on rent exponents of partitioning and placement
Proceedings of the 2001 international workshop on System-level interconnect prediction
On partitioning vs. placement rent properties
Proceedings of the 2001 international workshop on System-level interconnect prediction
On rent's rule for rectangular regions
Proceedings of the 2001 international workshop on System-level interconnect prediction
A differential equation for placement analysis
IEEE Transactions on Very Large Scale Integration (VLSI) Systems - System Level Design
A stochastic model for the interconnection topology of digital circuits
IEEE Transactions on Very Large Scale Integration (VLSI) Systems - System Level Design
A comparison of various terminal-gate relationships for interconnect prediction in VLSI circuits
IEEE Transactions on Very Large Scale Integration (VLSI) Systems - Special section on system-level interconnect prediction (SLIP)
A priori wire length distribution models with multiterminal nets
IEEE Transactions on Very Large Scale Integration (VLSI) Systems - Special section on system-level interconnect prediction (SLIP)
Assessment of on-chip wire-length distribution models
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
The circuit and physical design of the POWER4 microprocessor
IBM Journal of Research and Development
Adaptable wire-length distribution with tunable occupation probability
Proceedings of the 2007 international workshop on System level interconnect prediction
Impact of interconnect length changes on effective materials properties (dielectric constant)
Proceedings of the 2007 international workshop on System level interconnect prediction
On two-layer brain-inspired hierarchical topologies – a rent's rule approach –
Transactions on High-Performance Embedded Architectures and Compilers IV
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This paper presents a comprehensive assessment of interconnect requirements in ULSI control logic circuitry and quantifies the agreement observed (1) between estimates and measurements of average wire-length in individual designs in real chips, and (2) between wire-length distributions provided by the models and wire-length distributions obtained from measurements. In this study, actual interconnect data is measured in ASIC-like control logic designs in the six functional units of the 1.3GHz POWER4. This paper compares interconnect measurements with estimates for control logic in individual designs, in functional units, and in the entire POWER4 core. The results presented in this paper show that the estimates are typically lower than the actual wire-length measurements. The results also show that the estimates of the total wire-length for all of the control logic in the POWER4 agree to within 31% of the total measured wire-length.