The ISPD98 circuit benchmark suite
ISPD '98 Proceedings of the 1998 international symposium on Physical design
Efficient representation of interconnection length distributions using generating polynomials
SLIP '00 Proceedings of the 2000 international workshop on System-level interconnect prediction
The interpretation and application of Rent's rule
IEEE Transactions on Very Large Scale Integration (VLSI) Systems - Special issue on system-level interconnect prediction
On partitioning vs. placement rent properties
Proceedings of the 2001 international workshop on System-level interconnect prediction
Multi-terminal nets do change conventional wire length distribution models
Proceedings of the 2001 international workshop on System-level interconnect prediction
GLS '99 Proceedings of the Ninth Great Lakes Symposium on VLSI
Generating synthetic benchmark circuits for evaluating CAD tools
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
On partitioning vs. placement rent properties
Proceedings of the 2001 international workshop on System-level interconnect prediction
Fast estimation of the partitioning rent characteristic using a recursive partitioning model
Proceedings of the 2003 international workshop on System-level interconnect prediction
Automatic Partitioning for Improved Placement and Routing in Complex Programmable Logic Devices
FPL '02 Proceedings of the Reconfigurable Computing Is Going Mainstream, 12th International Conference on Field-Programmable Logic and Applications
A comparison of various terminal-gate relationships for interconnect prediction in VLSI circuits
IEEE Transactions on Very Large Scale Integration (VLSI) Systems - Special section on system-level interconnect prediction (SLIP)
Interconnect-based system-level energy and power prediction to guide architecture exploration
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Assessment of on-chip wire-length distribution models
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Predicting interconnect requirements in ultra-large-scale integrated control logic circuitry
Proceedings of the 2005 international workshop on System level interconnect prediction
ISQED '06 Proceedings of the 7th International Symposium on Quality Electronic Design
IBM Journal of Research and Development - POWER5 and packaging
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
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A priori wirelength estimates are based on a terminal-gate relationship known as Rent's rule. Conventional models apply Rent's rule in 2D on square or diamond-shaped regions. However, more advanced applications of wirelength estimation require the use of Rent's rule on layout regions with different shapes. In this paper, we systematically study the layout Rent parameters of rectangular regions in a 2D layout medium. For this purpose, we derive a theoretical model for the pin versus gate relationship for layout regions of any given shape. Using this model to find an estimation of the layout Rent parameters of rectangular regions with a given aspect ratio, we show that there is a significant dependency of the Rent coefficient on that aspect ratio. We experimentally verify these results with synthetic, as well as industrial benchmark circuits.Furthermore, our model relates the layout Rent parameters of a circuit to its intrinsic partitioning properties. This leads to a fundamental limit on the value of the layout Rent exponent for circuits, embedded in a 2D layout medium.