Simultaneous functional-unit binding and floorplanning
ICCAD '94 Proceedings of the 1994 IEEE/ACM international conference on Computer-aided design
Layout-driven RTL binding techniques for high-level synthesis using accurate estimators
ACM Transactions on Design Automation of Electronic Systems (TODAES)
On rent's rule for rectangular regions
Proceedings of the 2001 international workshop on System-level interconnect prediction
Simultaneous Scheduling, Binding and Floorplanning in High-level Synthesis
VLSID '98 Proceedings of the Eleventh International Conference on VLSI Design: VLSI for Signal Processing
The future of interconnection technology
IBM Journal of Research and Development
A data-centric approach to high-level synthesis
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
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We present an assessment of a priori stochastic wirelength estimation as a viable technique for evaluating the interconnect requirements of designs explored in RTL datapath synthesis. The model estimates the wirelength requirements of a gate level netlist a priori, based on Rentian parameters extracted dynamically from RTL netlists. Experimental results indicate that the wirelength estimates of our dynamic Rent parameter extraction method are in agreement within an average of 3.96% to those obtained from designs synthesized by a commercial place-and-route tool, while offering an average speedup of 278% over physical synthesis, suggesting that stochastic wirelength estimation methods are a viable approach to guide design space exploration in high-level synthesis.