Performance-driven placement of cell based IC's
DAC '89 Proceedings of the 26th ACM/IEEE Design Automation Conference
Average interconnection length and interconnection distribution based on rent's rule
DAC '89 Proceedings of the 26th ACM/IEEE Design Automation Conference
The role of timing verification in layout synthesis
DAC '91 Proceedings of the 28th ACM/IEEE Design Automation Conference
Chortle: a technology mapping program for lookup table-based field programmable gate arrays
DAC '90 Proceedings of the 27th ACM/IEEE Design Automation Conference
Dynamic prediction of critical paths and nets for constructive timing-driven placement
DAC '91 Proceedings of the 28th ACM/IEEE Design Automation Conference
3D scheduling: high-level synthesis with floorplanning
DAC '91 Proceedings of the 28th ACM/IEEE Design Automation Conference
Simultaneous functional-unit binding and floorplanning
ICCAD '94 Proceedings of the 1994 IEEE/ACM international conference on Computer-aided design
100-hour design cycle: a test case
EURO-DAC '94 Proceedings of the conference on European design automation
ICCAD '95 Proceedings of the 1995 IEEE/ACM international conference on Computer-aided design
A grid-based approach for connectivity binding with geometric costs
ICCAD '93 Proceedings of the 1993 IEEE/ACM international conference on Computer-aided design
A module area estimator for VLSI layout
DAC '88 Proceedings of the 25th ACM/IEEE Design Automation Conference
A tutorial on logic synthesis for lookup-table based FPGAs
ICCAD '92 Proceedings of the 1992 IEEE/ACM international conference on Computer-aided design
Accurate layout area and delay modeling for system level design
ICCAD '92 Proceedings of the 1992 IEEE/ACM international conference on Computer-aided design
DAC '86 Proceedings of the 23rd ACM/IEEE Design Automation Conference
Area and Timing Estimation for Lookup Table Based FPGAs
EDTC '96 Proceedings of the 1996 European conference on Design and Test
Chip layout optimization using critical path weighting
DAC '84 Proceedings of the 21st Design Automation Conference
On the relation between wire length distributions and placement of logic on master slice ICs
DAC '84 Proceedings of the 21st Design Automation Conference
EMPIRICAL EVALUATION OF MULTILEVEL LOGIC MINIMIZATION TOOLS FOR A FIELD-PROGRAMMABLE GATE ARRAY TECHNOLOGY
Statistical performance-driven module binding in high-level synthesis
Proceedings of the 11th international symposium on System synthesis
Automated design synthesis and partitioning for adaptive reconfigurable hardware
Hardware implementation of intelligent systems
Interconnect-aware high-level synthesis for low power
Proceedings of the 2002 IEEE/ACM international conference on Computer-aided design
Assignment-Space Exploration Approach to Concurrent Data-Path/Floorplan Synthesis
ICCD '00 Proceedings of the 2000 IEEE International Conference on Computer Design: VLSI in Computers & Processors
Quality of EDA CAD Tools: Definitions, Metrics and Directions
ISQED '00 Proceedings of the 1st International Symposium on Quality of Electronic Design
Simultaneous floorplanning and resource binding: a probabilistic approach
Proceedings of the 2005 Asia and South Pacific Design Automation Conference
ISQED '06 Proceedings of the 7th International Symposium on Quality Electronic Design
An integrated approach to thermal management in high-level synthesis
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Power-driven simultaneous resource binding and floorplanning: a probabilistic approach
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Proceedings of the 21st edition of the great lakes symposium on Great lakes symposium on VLSI
Towards layout-friendly high-level synthesis
Proceedings of the 2012 ACM international symposium on International Symposium on Physical Design
Fast and effective placement and routing directed high-level synthesis for FPGAs
Proceedings of the 2014 ACM/SIGDA international symposium on Field-programmable gate arrays
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The importance of effective and efficient accounting of layout effects is well established in High-Level Synthesis (HLS), since it allows more realistic exploration of the design space and the generation of solutions with predictable metrics. This feature is highly desirable in order to avoid unnecessary iterations through the design process. In this article, we address the problem of layout-driven register-transfer-level (RTL) binding as this step has a direct relevance to the final performance of the design. By producing not only an RTL design but also an approximate physical topology of the chip-level implementation, we ensure that the solution will perform at the predicted metric once implemented, thus avoiding unnecessary delays in the design process.