3D scheduling: high-level synthesis with floorplanning
DAC '91 Proceedings of the 28th ACM/IEEE Design Automation Conference
Simultaneous functional-unit binding and floorplanning
ICCAD '94 Proceedings of the 1994 IEEE/ACM international conference on Computer-aided design
Recent developments in high-level synthesis
ACM Transactions on Design Automation of Electronic Systems (TODAES)
Layout-driven RTL binding techniques for high-level synthesis using accurate estimators
ACM Transactions on Design Automation of Electronic Systems (TODAES)
The Synthesis Approach to Digital System Design
The Synthesis Approach to Digital System Design
Statistical Analysis Driven Synthesis of Asynchronous Systems
ICCD '05 Proceedings of the 2005 International Conference on Computer Design
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As the geometrical design rules of VLSIs become finer into the order of deep sub-micron, the impact of wires to VLSI performance becomes larger relatively to the other components, and their estimation at RT-level description and performance-driven data-path synthesis need explicit connectivity information about RT-level architecture and its floorplan. In this paper, an assignment-driven approach to the data-path synthesis incorporated with one-dimensional floorplanning is proposed. In our approach, scheduling and one-dimensional floorplanning, both of which are driven by iteratively generated functional unit and register assignment (binding), are performed fully concurrently. Pseudo-branch-and-bound assignment space exploration is adopted for generating assignments in this pilot system.