Communicating sequential processes
Communicating sequential processes
Fuzzy sets, uncertainty, and information
Fuzzy sets, uncertainty, and information
Statecharts: A visual formalism for complex systems
Science of Computer Programming
Specification partitioning for system design
DAC '92 Proceedings of the 29th ACM/IEEE Design Automation Conference
Specification and design of embedded systems
Specification and design of embedded systems
The Verilog hardware description language (4th ed.)
The Verilog hardware description language (4th ed.)
High-Level VLSI Synthesis
Implementing fuzzy control systems using VHDL and statecharts
EURO-DAC '96/EURO-VHDL '96 Proceedings of the conference on European design automation
Layout-driven RTL binding techniques for high-level synthesis using accurate estimators
ACM Transactions on Design Automation of Electronic Systems (TODAES)
System-level exploration with SpecSyn
DAC '98 Proceedings of the 35th annual Design Automation Conference
A model for system-level timed analysis and profiling
Proceedings of the conference on Design, automation and test in Europe
Readings in hardware/software co-design
Specification and Design of Embedded Hardware-Software Systems
IEEE Design & Test
Architectural exploration for datapaths with memory hierarchy
EDTC '95 Proceedings of the 1995 European conference on Design and Test
Area and Timing Estimation for Lookup Table Based FPGAs
EDTC '96 Proceedings of the 1996 European conference on Design and Test
A Flexible Model for Evaluating the Behavior of Hardware/Software Systems
CODES '97 Proceedings of the 5th International Workshop on Hardware/Software Co-Design
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
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