Statemate: a working environment for the development of complex reactive systems
ICSE '88 Proceedings of the 10th international conference on Software engineering
An engineering environment for hardware/software co-simulation
DAC '92 Proceedings of the 29th ACM/IEEE Design Automation Conference
CHOP: A constraint-driven system-level partitioner
DAC '91 Proceedings of the 28th ACM/IEEE Design Automation Conference
Incremental tree height reduction for high level synthesis
DAC '91 Proceedings of the 28th ACM/IEEE Design Automation Conference
High-level synthesis: introduction to chip and system design
High-level synthesis: introduction to chip and system design
Specification partitioning for system design
DAC '92 Proceedings of the 29th ACM/IEEE Design Automation Conference
Synthesis and simulation of digital systems containing interacting hardware and software components
DAC '92 Proceedings of the 29th ACM/IEEE Design Automation Conference
Specification and design of embedded systems
Specification and design of embedded systems
Protocol generation for communication channels
DAC '94 Proceedings of the 31st annual Design Automation Conference
100-hour design cycle: a test case
EURO-DAC '94 Proceedings of the conference on European design automation
A binary-constraint search algorithm for minimizing hardware during hardware/software partitioning
EURO-DAC '94 Proceedings of the conference on European design automation
A method for partitioning UNITY language in hardware and software
EURO-DAC '94 Proceedings of the conference on European design automation
A component selection algorithm for high-performance pipelines
EURO-DAC '94 Proceedings of the conference on European design automation
Incremental hardware estimation during hardware/software functional partitioning
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
A memory selection algorithm for high-performance pipelines
EURO-DAC '95/EURO-VHDL '95 Proceedings of the conference on European design automation
Clustering for improved system-level functional partitioning
ISSS '95 Proceedings of the 8th international symposium on System synthesis
Procedure exlining: a transformation for improved system and behavioral synthesis
ISSS '95 Proceedings of the 8th international symposium on System synthesis
Port calling: a transformation for reducing I/O during multi-package functional partitioning
ISSS '97 Proceedings of the 10th international symposium on System synthesis
Design of system interface modules
ICCAD '92 Proceedings of the 1992 IEEE/ACM international conference on Computer-aided design
Synthesis by delayed binding of decisions
DAC '85 Proceedings of the 22nd ACM/IEEE Design Automation Conference
Communicating sequential processes
Communications of the ACM
High-Level Synthesis for Real-Time Digital Signal Processing
High-Level Synthesis for Real-Time Digital Signal Processing
A Hardware-Software Codesign Methodology for DSP Applications
IEEE Design & Test
Hardware-Software Cosynthesis for Digital Systems
IEEE Design & Test
Hardware-Software Cosynthesis for Microcontrollers
IEEE Design & Test
Specification and Design of Embedded Hardware-Software Systems
IEEE Design & Test
Automatic Extraction of Functional Parallelism from Ordinary Programs
IEEE Transactions on Parallel and Distributed Systems
Synthesizing Converters Between Finite State Protocols
ICCD '91 Proceedings of the 1991 IEEE International Conference on Computer Design on VLSI in Computer & Processors
Software estimation using a generic-processor model
EDTC '95 Proceedings of the 1995 European conference on Design and Test
Model Refinement for Hardware-Software Codesign
EDTC '96 Proceedings of the 1996 European conference on Design and Test
Procedure cloning: a transformation for improved system-level functional partitioning
EDTC '97 Proceedings of the 1997 European conference on Design and Test
Partitioning and Exploration Strategies in the TOSCA Co-Design Flow
CODES '96 Proceedings of the 4th International Workshop on Hardware/Software Co-Design
A Comparison of Functional and Structural Partitioning
ISSS '96 Proceedings of the 9th international symposium on System synthesis
Hardware/Software Partitioning with Iterative Improvement Heuristics
ISSS '96 Proceedings of the 9th international symposium on System synthesis
A methodology for control-dominated systems codesign
CODES '94 Proceedings of the 3rd international workshop on Hardware/software co-design
Configuration-level hardware/software partitioning for real-time embedded systems
CODES '94 Proceedings of the 3rd international workshop on Hardware/software co-design
CODES '94 Proceedings of the 3rd international workshop on Hardware/software co-design
Flexible modeling environment for embedded systems design
CODES '94 Proceedings of the 3rd international workshop on Hardware/software co-design
SpecCharts: a VHDL front-end for embedded systems
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
ESL Design and Verification: A Prescription for Electronic System Level Methodology
ESL Design and Verification: A Prescription for Electronic System Level Methodology
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System-level design issues are gaining increasing attention, as behavioral synthesis tools and ethodologies mature. We present the SpecSyn system-level design environment, which supports the new specify- explore-refine (SER) design paradigm. This three-step approach to design includes precise specification of system functionality, rapid exploration of numerous system-level design options, and refinement of the specification into one reflecting the chosen option. A system-level design option consists of an allocation of system components, such as standard and custom processors, memories, and buses and a partitioning of functionality among those components. After refinement, the functionality assigned to each component can then be synthesized to hardware or compiled to software. We describe the issues and approaches for each part of the SpecSyn environment. The new paradigm and environment are expected to lead to a more than ten times reduction in design time, and our experiments support this expectation.