Introduction to algorithms
CHOP: A constraint-driven system-level partitioner
DAC '91 Proceedings of the 28th ACM/IEEE Design Automation Conference
Specification partitioning for system design
DAC '92 Proceedings of the 29th ACM/IEEE Design Automation Conference
Specification and design of embedded systems
Specification and design of embedded systems
Experience with image compression chip design using unified system construction tools
DAC '94 Proceedings of the 31st annual Design Automation Conference
A method for partitioning UNITY language in hardware and software
EURO-DAC '94 Proceedings of the conference on European design automation
Incremental hardware estimation during hardware/software functional partitioning
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Procedure exlining: a transformation for improved system and behavioral synthesis
ISSS '95 Proceedings of the 8th international symposium on System synthesis
Partitioning of VLSI circuits and systems
DAC '96 Proceedings of the 33rd annual Design Automation Conference
A Model and Methodology for Hardware-Software Codesign
IEEE Design & Test
Hardware-Software Cosynthesis for Digital Systems
IEEE Design & Test
Hardware-Software Cosynthesis for Microcontrollers
IEEE Design & Test
Towards a Model for Hardware and Software Functional Partitioning
CODES '96 Proceedings of the 4th International Workshop on Hardware/Software Co-Design
A methodology for control-dominated systems codesign
CODES '94 Proceedings of the 3rd international workshop on Hardware/software co-design
VHDL system-level specification and partitioning in a hardware/software co-synthesis environment
CODES '94 Proceedings of the 3rd international workshop on Hardware/software co-design
I/O and performance tradeoffs with the FunctionBus during multi-FPGA partitioning
FPGA '97 Proceedings of the 1997 ACM fifth international symposium on Field-programmable gate arrays
Port calling: a transformation for reducing I/O during multi-package functional partitioning
ISSS '97 Proceedings of the 10th international symposium on System synthesis
A three-step approach to the functional partitioning of large behavioral processes
Proceedings of the 11th international symposium on System synthesis
Procedure cloning: a transformation for improved system-level functional partitioning
ACM Transactions on Design Automation of Electronic Systems (TODAES)
FSMD functional partitioning for low power
DATE '99 Proceedings of the conference on Design, automation and test in Europe
Readings in hardware/software co-design
Procedure cloning: a transformation for improved system-level functional partitioning
EDTC '97 Proceedings of the 1997 European conference on Design and Test
Modifying Min-Cut for Hardware and Software Functional Partitioning
CODES '97 Proceedings of the 5th International Workshop on Hardware/Software Co-Design
Battery-aware code partitioning for a text to speech system
Proceedings of the conference on Design, automation and test in Europe: Proceedings
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
| Hi-index | 0.00 |
Incorporating functional partitioning into a synthesis methodology leads to several important advantages. In functional partitioning, we first partition a functional specification into smaller sub-specifications and then synthesize structure for each, in contrast to the current approach of first synthesizing structure for the entire specification and then partitioning that structure. One advantage is that of greatly improved partitioning among a given set of packages with size and I/O constraints, such as FPGA's or ASIC blocks, resulting in better performance and far fewer required packages. A second advantage is that of greatly reduced synthesis runtimes. We present results of experiments demonstrating these important advantages, leading to the conclusion that further research focus on functional partitioning can lead to improved quality and practicality of synthesis environments.