STATEMATE: A Working Environment for the Development of Complex Reactive Systems
IEEE Transactions on Software Engineering
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DAC '92 Proceedings of the 29th ACM/IEEE Design Automation Conference
IEEE Design & Test
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IEEE Design & Test
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IEEE Design & Test
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IEEE Design & Test
Cosimulation of real-time control systems
EURO-DAC '95/EURO-VHDL '95 Proceedings of the conference on European design automation
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EURO-DAC '95/EURO-VHDL '95 Proceedings of the conference on European design automation
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EURO-DAC '95/EURO-VHDL '95 Proceedings of the conference on European design automation
Clustering for improved system-level functional partitioning
ISSS '95 Proceedings of the 8th international symposium on System synthesis
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ISSS '95 Proceedings of the 8th international symposium on System synthesis
ACM Transactions on Design Automation of Electronic Systems (TODAES)
Procedure cloning: a transformation for improved system-level functional partitioning
ACM Transactions on Design Automation of Electronic Systems (TODAES)
Design of embedded systems: formal models, validation, and synthesis
Readings in hardware/software co-design
Readings in hardware/software co-design
Incremental hardware estimation during hardware/software functional partitioning
Readings in hardware/software co-design
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Specification and Design of Embedded Hardware-Software Systems
IEEE Design & Test
Procedure cloning: a transformation for improved system-level functional partitioning
EDTC '97 Proceedings of the 1997 European conference on Design and Test
Towards a Model for Hardware and Software Functional Partitioning
CODES '96 Proceedings of the 4th International Workshop on Hardware/Software Co-Design
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ISSS '96 Proceedings of the 9th international symposium on System synthesis
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
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This paper presents a methodology and a supporting framework for the design of systems composed of hardware and software modules. The aim is to define an approach, tailored for control-oriented applications, to manage system cospecification, high-level partitioning, hw/sw tradeoffs and cosynthesis. The main goals are always to improve design time and costs by supporting a flexible architectural exploration and to achieve a smooth integration within standard industrial design environments.Our research effort focuses on fulfilling the goal of linking high-level specifications to efficient and cost-effective hw/sw implementations, by investigating techniques such as synchronous cospecification styles, direct machine code generation as well as exploiting the capability of commercial VHDL synthesizers.