VLSI array processors
3D scheduling: high-level synthesis with floorplanning
DAC '91 Proceedings of the 28th ACM/IEEE Design Automation Conference
Simultaneous functional-unit binding and floorplanning
ICCAD '94 Proceedings of the 1994 IEEE/ACM international conference on Computer-aided design
A unified design methodology for CMOS tapered buffers
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Register allocation and binding for low power
DAC '95 Proceedings of the 32nd annual ACM/IEEE Design Automation Conference
Power-profiler: optimizing ASICs power consumption at the behavioral level
DAC '95 Proceedings of the 32nd annual ACM/IEEE Design Automation Conference
Simultaneous scheduling and binding for power minimization during microarchitecture synthesis
ISLPED '95 Proceedings of the 1995 international symposium on Low power design
High-level synthesis techniques for reducing the activity of functional units
ISLPED '95 Proceedings of the 1995 international symposium on Low power design
Digital integrated circuits: a design perspective
Digital integrated circuits: a design perspective
Low-power architectural synthesis and the impact of exploiting locality
Journal of VLSI Signal Processing Systems - Special issue on technologies for wireless computing
Layout-driven RTL binding techniques for high-level synthesis using accurate estimators
ACM Transactions on Design Automation of Electronic Systems (TODAES)
A flexible datapath allocation method for architectural synthesis
ACM Transactions on Design Automation of Electronic Systems (TODAES)
Unifying behavioral synthesis and physical design
Proceedings of the 37th Annual Design Automation Conference
Automating RT-level operand isolation to minimize power consumption in datapaths
DATE '00 Proceedings of the conference on Design, automation and test in Europe
Modeling and minimization of interconnect energy dissipation in nanometer technologies
Proceedings of the 38th annual Design Automation Conference
Proceedings of the 39th annual Design Automation Conference
Algorithms for VLSI Physical Design Automation
Algorithms for VLSI Physical Design Automation
High-Level Power Analysis and Optimization
High-Level Power Analysis and Optimization
Bus optimization for low-power data path synthesis based on network flow method
Proceedings of the 2000 IEEE/ACM international conference on Computer-aided design
A bus energy model for deep submicron technology
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Profile-Driven Behavioral Synthesis for Low-Power VLSI Systems
IEEE Design & Test
ICCD '96 Proceedings of the 1996 International Conference on Computer Design, VLSI in Computers and Processors
Microarchitectural Synthesis of Performance-Constrained, Low-Power VLSI Designs
ICCS '94 Proceedings of the1994 IEEE International Conference on Computer Design: VLSI in Computer & Processors
A linear-time heuristic for improving network partitions
DAC '82 Proceedings of the 19th Design Automation Conference
Simultaneous Scheduling, Binding and Floorplanning in High-level Synthesis
VLSID '98 Proceedings of the Eleventh International Conference on VLSI Design: VLSI for Signal Processing
Interconnect Energy Dissipation in High-Speed ULSI Circuits
ASP-DAC '02 Proceedings of the 2002 Asia and South Pacific Design Automation Conference
SCALP: an iterative-improvement-based low-power data path synthesis system
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Controller-based power management for control-flow intensive designs
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
High-level synthesis of low-power control-flow intensive circuits
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Interconnect performance estimation models for design planning
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Architectural energy optimization by bus splitting
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
An interconnect energy model considering coupling effects
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Optimizing power using transformations
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Binding, Allocation and Floorplanning in Low Power High-Level Synthesis
Proceedings of the 2003 IEEE/ACM international conference on Computer-aided design
A High-level Interconnect Power Model for Design Space Exploration
Proceedings of the 2003 IEEE/ACM international conference on Computer-aided design
Predictable design of low power systems by pre-implementation estimation and optimization
Proceedings of the 2004 Asia and South Pacific Design Automation Conference
Incremental exploration of the combined physical and behavioral design space
Proceedings of the 42nd annual Design Automation Conference
TAPHS: thermal-aware unified physical-level and high-level synthesis
ASP-DAC '06 Proceedings of the 2006 Asia and South Pacific Design Automation Conference
Simultaneous floorplanning and resource binding: a probabilistic approach
Proceedings of the 2005 Asia and South Pacific Design Automation Conference
On-Chip Communication Architectures: System on Chip Interconnect
On-Chip Communication Architectures: System on Chip Interconnect
Guaranteeing performance yield in high-level synthesis
Proceedings of the 2006 IEEE/ACM international conference on Computer-aided design
An integrated approach to thermal management in high-level synthesis
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Power optimization with power islands synthesis
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Switching activity models for power estimation in FPGA multipliers
ARC'07 Proceedings of the 3rd international conference on Reconfigurable computing: architectures, tools and applications
A global interconnect reduction technique during high level synthesis
Proceedings of the 2010 Asia and South Pacific Design Automation Conference
Control for power gating of wires
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Power-driven simultaneous resource binding and floorplanning: a probabilistic approach
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Modeling and simulation in a formal design framework
Proceedings of the 6th Balkan Conference in Informatics
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Interconnects (wires, buffers, clock distribution networks, multiplexers and busses) consume a significant fraction of total circuit power. In this work, we demonstrate the importance of optimizing on-chip interconnects for power during high-level synthesis. We present a methodology to integrate interconnect power optimization into high-level synthesis. Our binding algorithm not only reduces power consumption in functional units and registers in the resultant register-transfer level (RTL) architecture, but also optimizes interconnects for power. We take physical design information into account for this purpose. To estimate interconnect power consumption accurately for deep sub-micron (DSM) technologies, wire coupling capacitance is taken into consideration. We observed that there is significant spurious (i.e., unnecessary) switching activity in the interconnects and propose techniques to reduce it. Compared to interconnect-unaware power-optimized circuits, our experimental results show that interconnect power can be reduced by 53.1% on an average, while reducing overall power by an average of 26.8% with 0.5% area overhead. Compared to area-optimized circuits, the interconnect power reduction is 72.9% and overall power reduction is 56.0% with 44.4% area overhead.