Scheduling and resource binding for low power
ISSS '95 Proceedings of the 8th international symposium on System synthesis
Fast high-level power estimation for control-flow intensive design
ISLPED '98 Proceedings of the 1998 international symposium on Low power electronics and design
Automatic nonlinear memory power modelling
Proceedings of the conference on Design, automation and test in Europe
Estimation of lower and upper bounds on the power consumption from scheduled data flow graphs
IEEE Transactions on Very Large Scale Integration (VLSI) Systems - Special issue on low power electronics and design
System level optimization and design space exploration for low power
Proceedings of the 14th international symposium on Systems synthesis
Behavioral Synthesis for low Power
ICCS '94 Proceedings of the1994 IEEE International Conference on Computer Design: VLSI in Computer & Processors
Interconnect-aware high-level synthesis for low power
Proceedings of the 2002 IEEE/ACM international conference on Computer-aided design
Simultaneous Scheduling, Binding and Floorplanning for Interconnect Power Optimization
VLSID '99 Proceedings of the 12th International Conference on VLSI Design - 'VLSI for the Information Appliance'
Moment-Based Power Estimation in Very Deep Submicron Technologies
Proceedings of the 2003 IEEE/ACM international conference on Computer-aided design
Binding, Allocation and Floorplanning in Low Power High-Level Synthesis
Proceedings of the 2003 IEEE/ACM international conference on Computer-aided design
| Hi-index | 0.00 |
Each year tens of billions of Dollars are wasted by the microelectronics industry because of missed deadlines and delayed design projects. These delays are partially due to design iterations many of which could have been avoided if the low level remifications of high level design decisions, at the Architecture- and Algorithmic-level would have been known before the time consuming and tedious RT- and lower level implementation started. In this contribution we present a System-level design flow and respective EDA support tools for low power designs. We analyze the requirements for such a design technology, which shifts more responsibility to the system architect. We exemplify this approach with a design flow for low power systems. The architecture of an Algorithm-level power estimation tool will be presented together with some use cases based on a EDA product which has been commercially developed from the research results of several collaborative projects funded by the Commission of the European Community.