Architectural power analysis: the dual bit type method
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Theoretical analysis of word-level switching activity in the presence of glitching and correlation
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Power Optimization and Synthesis at Behavioral and System Levels Using Formal Methods
Power Optimization and Synthesis at Behavioral and System Levels Using Formal Methods
Coupling-aware high-level interconnect synthesis for low power
Proceedings of the 2002 IEEE/ACM international conference on Computer-aided design
Simultaneous Subthreshold and Gate-Oxide Tunneling Leakage Current Analysis in Nanometer CMOS Design
ISQED '03 Proceedings of the 4th International Symposium on Quality Electronic Design
IEEE Transactions on Signal Processing
Analytical estimation of signal transition activity from word-level statistics
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
An analytical approach for dynamic range estimation
Proceedings of the 41st annual Design Automation Conference
Predictable design of low power systems by pre-implementation estimation and optimization
Proceedings of the 2004 Asia and South Pacific Design Automation Conference
Dynamic range estimation for nonlinear systems
Proceedings of the 2004 IEEE/ACM International conference on Computer-aided design
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The significant power optimization possibilities in the early stagesof the design flow advice the use of energy evaluation techniquesat high levels of abstraction. With this aim, the present work addressesthe estimation of the energy consumption in very deep submicrontechnologies. Using the characterization of the probabilitydensity function with a projection in an orthogonal polynomialbase, and a symbolic propagation mechanism, a technique is presentedto estimate the dynamic and static power consumption indigital systems. The proposed approach has been validated withcircuits and excitations from realistic applications. Comparisonswith reference transistor and bit level simulations are reported inorder to asses the the accuracy of the technique.