Design of a high-throughput low-power IS95 Viterbi decoder
Proceedings of the 39th annual Design Automation Conference
Predictable design of low power systems by pre-implementation estimation and optimization
Proceedings of the 2004 Asia and South Pacific Design Automation Conference
Leakage Power Driven Behavioral Synthesis of Pipelined Datapaths
ISVLSI '05 Proceedings of the IEEE Computer Society Annual Symposium on VLSI: New Frontiers in VLSI Design
Physical design implementation of segmented buses to reduce communication energy
ASP-DAC '06 Proceedings of the 2006 Asia and South Pacific Design Automation Conference
Design of a 20-Mb/s 256-state viterbi decoder
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
A game theoretic approach for power optimization during behavioral synthesis
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
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Interconnect power dissipation is becoming a major component of power consumption in a circuit especially in sub-micron technologies. The energy dissipated by a particular interconnection link is determined by the switching activity on that link and also on its capacitance. The switching activity is determined by the schedule and binding, whereas the capacitance is determined by the floorplan. Scheduling, binding and floorplanning are closely inter-related. A simultaneous scheduling, binding and floorplanning algorithm is presented which attempts to minimize interconnect energy dissipation. In comparison to a traditional approach which separates high-level synthesis from physical design, our algorithm is able to make these stages interact very closely, resulting in solutions with lower power, latency and area. We show that it is possible to reduce the interconnect energy dissipation by upto around 60 percent for high-level synthesis benchmark circuits.