Digital integrated circuits: a design perspective
Digital integrated circuits: a design perspective
Low-power architectural synthesis and the impact of exploiting locality
Journal of VLSI Signal Processing Systems - Special issue on technologies for wireless computing
MOCSYN: multiobjective core-based single-chip system synthesis
DATE '99 Proceedings of the conference on Design, automation and test in Europe
Modeling and minimization of interconnect energy dissipation in nanometer technologies
Proceedings of the 38th annual Design Automation Conference
Proceedings of the 39th annual Design Automation Conference
High-Level Power Analysis and Optimization
High-Level Power Analysis and Optimization
Bus optimization for low-power data path synthesis based on network flow method
Proceedings of the 2000 IEEE/ACM international conference on Computer-aided design
A bus energy model for deep submicron technology
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Interconnect-aware high-level synthesis for low power
Proceedings of the 2002 IEEE/ACM international conference on Computer-aided design
Simultaneous Scheduling, Binding and Floorplanning in High-level Synthesis
VLSID '98 Proceedings of the Eleventh International Conference on VLSI Design: VLSI for Signal Processing
Interconnect Energy Dissipation in High-Speed ULSI Circuits
ASP-DAC '02 Proceedings of the 2002 Asia and South Pacific Design Automation Conference
The future of interconnection technology
IBM Journal of Research and Development
SCALP: an iterative-improvement-based low-power data path synthesis system
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Register transfer level power optimization with emphasis on glitch analysis and reduction
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Interconnect performance estimation models for design planning
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Exact and efficient crosstalk estimation
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
An interconnect energy model considering coupling effects
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Replacing global wires with an on-chip network: a power analysis
ISLPED '05 Proceedings of the 2005 international symposium on Low power electronics and design
Exploiting last idle periods of links for network power management
Proceedings of the 5th ACM international conference on Embedded software
Compiler-directed proactive power management for networks
Proceedings of the 2005 international conference on Compilers, architectures and synthesis for embedded systems
Delay and Power Estimation Models of Low-Swing Interconnects for Design Planning
GLSVLSI '06 Proceedings of the 16th ACM Great Lakes symposium on VLSI
On-Chip Communication Architectures: System on Chip Interconnect
On-Chip Communication Architectures: System on Chip Interconnect
INTACTE: an interconnect area, delay, and energy estimation tool for microarchitectural explorations
CASES '07 Proceedings of the 2007 international conference on Compilers, architecture, and synthesis for embedded systems
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In this paper, we present a high-level power model toestimate the power consumption in semi-global and global interconnects.Such interconnects are used for communications between logic modules,clock distribution networks, and power supply rails. The main purposeof our model is to set forward a simple methodology to efficiently obtainfirst-order estimates of interconnect power in early stages of the designprocess. Hence, the objective is to provide designers and/or high-leveldesign automation tools with a way to quickly explore the design spaceand weed out architectures whose interconnect power requirements donot meet the allocated power budget. In addition to switching power,which includes inter-wire coupling, our model also considers power dueto vias and repeaters. Our experimental results show that in comparisonto an accurate low-level model, the error in our method in estimatingtotal switching power is only 6% (while the speedup is three-to-fourorders of magnitude), and an estimate of the numbers of vias (hence, viapower) is within 3% agreement of that obtained for designs synthesizedby commercial tools. Furthermore, we develop a probabilistic segmentlength distribution model for cases in which Rent's rule is inadequate. Byanalyzing the netlists of a set of complex designs, we have been able tovalidate our segment length distribution model. The novelty of this worklies in the introduction of a high-level interconnect modeling methodologyin which it is possible to efficiently compute all the major sources ofpower consumption in interconnects and hence, enable interconnect-aware,high-level design space exploration.