Improved delay prediction for on-chip buses
Proceedings of the 36th annual ACM/IEEE Design Automation Conference
Fast and accurate estimation of floorplans in logic/high-level synthesis
GLSVLSI '00 Proceedings of the 10th Great Lakes symposium on VLSI
Behavior-to-placed RTL synthesis with performance-driven placement
Proceedings of the 2001 IEEE/ACM international conference on Computer-aided design
Interconnect-aware high-level synthesis for low power
Proceedings of the 2002 IEEE/ACM international conference on Computer-aided design
Binding, Allocation and Floorplanning in Low Power High-Level Synthesis
Proceedings of the 2003 IEEE/ACM international conference on Computer-aided design
A High-level Interconnect Power Model for Design Space Exploration
Proceedings of the 2003 IEEE/ACM international conference on Computer-aided design
Incremental exploration of the combined physical and behavioral design space
Proceedings of the 42nd annual Design Automation Conference
ISQED '06 Proceedings of the 7th International Symposium on Quality Electronic Design
Layout driven data communication optimization for high level synthesis
Proceedings of the conference on Design, automation and test in Europe: Proceedings
An integrated approach to thermal management in high-level synthesis
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
A new methodology of integrating high level synthesis and floorplan for soc design
ICESS'05 Proceedings of the Second international conference on Embedded Software and Systems
Fast and effective placement and routing directed high-level synthesis for FPGAs
Proceedings of the 2014 ACM/SIGDA international symposium on Field-programmable gate arrays
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With small device features in sub-micron technologies, interconnection delays play a dominant part in cycle time. Therefore, it is important to consider the impact of physical design during high level synthesis. In this paper, an efficient floorplanning algorithm which takes into account the effect of interconnect delays on the overall cycle time of a given schedule is presented. A simultaneous scheduling, binding and floorplanning algorithm is also presented. In comparison to a traditional approach which separates high-level synthesis from physical design, our algorithm is able to make these stages interact very closely, resulting in solutions with lower latency and area. In addition, a detailed model is considered, taking into account multiplexor and register areas and delays.