Layout driven data communication optimization for high level synthesis

Authors:
Ryan Kastner;Wenrui Gong;Xin Hao;Forrest Brewer;Adam Kaplan;Philip Brisk;Majid Sarrafzadeh
Affiliations:
University of California, Santa Barbara;University of California, Santa Barbara;University of California, Santa Barbara;University of California, Santa Barbara;University of California, Los Angeles;University of California, Los Angeles;University of California, Los Angeles
Venue:
Proceedings of the conference on Design, automation and test in Europe: Proceedings
Year:
2006

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Abstract

High level synthesis transformations play a major part in shaping the properties of the final circuit. However, most optimizations are performed without much knowledge of the final circuit layout. In this paper, we present a physically aware design flow for mapping high level application specifications to a synthesizable register transfer level hardware description. We study the problem of optimizing the data communication of the variables in the application specification. Our algorithm uses floorplan information that guides the optimization. We develop a simple, yet effective, incremental floorplanner to handle the perturbations caused by the data communication optimization. We show that the proposed techniques can reduce the wirelength of the final design, while maintaining a legal floorplan with the same area as the initial floorplan.