Communicating sequential processes
Communicating sequential processes
Effective compiler support for predicated execution using the hyperblock
MICRO 25 Proceedings of the 25th annual international symposium on Microarchitecture
Advanced compiler design and implementation
Advanced compiler design and implementation
Adapting software pipelining for reconfigurable computing
CASES '00 Proceedings of the 2000 international conference on Compilers, architecture, and synthesis for embedded systems
Attacking the semantic gap between application programming languages and configurable hardware
FPGA '01 Proceedings of the 2001 ACM/SIGDA ninth international symposium on Field programmable gate arrays
Conversion of control dependence to data dependence
POPL '83 Proceedings of the 10th ACM SIGACT-SIGPLAN symposium on Principles of programming languages
Synthesizing RTL Hardware from Java Byte Codes
FPL '01 Proceedings of the 11th International Conference on Field-Programmable Logic and Applications
FCCM '99 Proceedings of the Seventh Annual IEEE Symposium on Field-Programmable Custom Computing Machines
Predicated Static Single Assignment
PACT '99 Proceedings of the 1999 International Conference on Parallel Architectures and Compilation Techniques
MPI: A Message-Passing Interface Standard
MPI: A Message-Passing Interface Standard
Data communication estimation and reduction for reconfigurable systems
Proceedings of the 40th annual Design Automation Conference
A design flow for partially reconfigurable hardware
ACM Transactions on Embedded Computing Systems (TECS)
Exploiting Program Branch Probabilities in Hardware Compilation
IEEE Transactions on Computers
Issues in debugging highly parallel FPGA-based applications derived from source code
ASP-DAC '03 Proceedings of the 2003 Asia and South Pacific Design Automation Conference
Layout driven data communication optimization for high level synthesis
Proceedings of the conference on Design, automation and test in Europe: Proceedings
Design, Debug, Deploy: The Creation of Configurable Computing Applications
Journal of Signal Processing Systems
Reconfigurable Computing: The Theory and Practice of FPGA-Based Computation
Reconfigurable Computing: The Theory and Practice of FPGA-Based Computation
Compiling for reconfigurable computing: A survey
ACM Computing Surveys (CSUR)
Optimized generation of memory structure in compiling window operations onto reconfigurable hardware
ARC'07 Proceedings of the 3rd international conference on Reconfigurable computing: architectures, tools and applications
Java bytecode to hardware made easy with bluespec system verilog
Proceedings of the 10th International Workshop on Java Technologies for Real-time and Embedded Systems
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Sea Cucumber (SC) is a synthesizing compiler for FPGAs that accepts Java class files as input (generated from Java source files) and that generates circuits that exploit the coarse- and fine-grained parallelism available in the input class files. Programmers determine the level of coarse-grained parallelism available by organizing their circuit as a set of inter-communicating, concurrent threads (using standard Java threads) that are implemented by SC as concurrent hardware. SC automatically extracts fine-grained parallelism from the body of each thread by processing the byte codes contained in the input class files and employs conventional compiler optimizations such as data-flow and controlflow graph analysis, dead-code elimination, constant folding, operation simplification, predicated static single assignment, if-conversion, hyperblock formation, etc. The resulting EDIF files can be processed using Xilinx place and route software to produce bitstreams that can be downloaded into FPGAs for execution.