Compilers: principles, techniques, and tools
Compilers: principles, techniques, and tools
The program dependence graph and its use in optimization
ACM Transactions on Programming Languages and Systems (TOPLAS)
High-level synthesis: introduction to chip and system design
High-level synthesis: introduction to chip and system design
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Advanced compiler design and implementation
Advanced compiler design and implementation
SpC: synthesis of pointers in C: application of pointer analysis to the behavioral synthesis from C
Proceedings of the 1998 IEEE/ACM international conference on Computer-aided design
Optimal temporal partitioning and synthesis for reconfigurable architectures
Proceedings of the conference on Design, automation and test in Europe
Synthesis and Optimization of Digital Circuits
Synthesis and Optimization of Digital Circuits
A Survey of Reconfigurable Computing Architectures
FPL '98 Proceedings of the 8th International Workshop on Field-Programmable Logic and Applications, From FPGAs to Computing Paradigm
Architectural Synthesis Techniques for Dynamically Reconfigurable Logic
FPL '96 Proceedings of the 6th International Workshop on Field-Programmable Logic, Smart Applications, New Paradigms and Compilers
Temporal Partitioning and Scheduling for Reconfigurable Computing
FCCM '98 Proceedings of the IEEE Symposium on FPGAs for Custom Computing Machines
Reconfigurable computing: a survey of systems and software
ACM Computing Surveys (CSUR)
Automated design synthesis and partitioning for adaptive reconfigurable hardware
Hardware implementation of intelligent systems
Compilation Increasing the Scheduling Scope for Multi-memory-FPGA-Based Custom Computing Machines
FPL '01 Proceedings of the 11th International Conference on Field-Programmable Logic and Applications
Sea Cucumber: A Synthesizing Compiler for FPGAs
FPL '02 Proceedings of the Reconfigurable Computing Is Going Mainstream, 12th International Conference on Field-Programmable Logic and Applications
Synthesizing RTL Hardware from Java Byte Codes
FPL '01 Proceedings of the 11th International Conference on Field-Programmable Logic and Applications
Compilation for FPGA-Based Reconfigurable Hardware
IEEE Design & Test
ARCHITECT-R: a system for reconfigurable robots design
Proceedings of the 2003 ACM symposium on Applied computing
Proceedings of the 1st conference on Computing frontiers
From C Programs to the Configure-Execute Model
DATE '03 Proceedings of the conference on Design, Automation and Test in Europe - Volume 1
Studying Energy Trade Offs in Offloading Computation/Compilation in Java-Enabled Mobile Devices
IEEE Transactions on Parallel and Distributed Systems
A Reconfigurable Processor Infrastructure for Accelerating Java Applications
IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences
Compiling for reconfigurable computing: A survey
ACM Computing Surveys (CSUR)
Fast hardware compilation of behaviors into an FPGA-based dynamic reconfigurable computing system
SBCCI'99 Proceedings of the XIIth conference on Integrated circuits and systems design
Jaguar: a compiler infrastructure for java reconfigurable computing
ICESS'05 Proceedings of the Second international conference on Embedded Software and Systems
Java bytecode to hardware made easy with bluespec system verilog
Proceedings of the 10th International Workshop on Java Technologies for Real-time and Embedded Systems
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This paper presents a new approach to synthesize to reconfigurable hardware (HW) user-specified regions of a program, under the assumption of "virtual HW" support. The automation of this approach is supported by a compiler front-end and by an HW compiler under development. The front-end starts from the Java bytecodes and, therefore, supports any language that can be compiled to the JVM (Java Virtual Machine) model. It extracts from the bytecodes all the dependencies inside and between basic blocks. This information is stored in representation graphs more suitable to efficiently exploit the existent parallelism in the program than those typically used in high-level synthesis. From the intermediate representations the HW compiler exploits the temporal partitions at the behavior level, resolves memory access conflicts, and generates the VHDL descriptions at register-transfer level that will be mapped into the reconfigurable HW devices.