The Function Processor: a data-driven processor array for irregular computations
Future Generation Computer Systems - Special issue: PARLE 91
DATE '00 Proceedings of the conference on Design, automation and test in Europe
A decade of reconfigurable computing: a visionary retrospective
Proceedings of the conference on Design, automation and test in Europe
A framework for reconfigurable computing: task scheduling and context management
IEEE Transactions on Very Large Scale Integration (VLSI) Systems - System Level Design
XPP-VC: A C Compiler with Temporal Partitioning for the PACT-XPP Architecture
FPL '02 Proceedings of the Reconfigurable Computing Is Going Mainstream, 12th International Conference on Field-Programmable Logic and Applications
Automatic Synthesis of Parallel Programs Targeted to Dynamically Reconfigurable Logic Arrays
FPL '95 Proceedings of the 5th International Workshop on Field-Programmable Logic and Applications
Architecture Design of Reconfigurable Pipelined Datapaths
ARVLSI '99 Proceedings of the 20th Anniversary Conference on Advanced Research in VLSI
FCCM '99 Proceedings of the Seventh Annual IEEE Symposium on Field-Programmable Custom Computing Machines
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Configware and morphware going mainstream
Journal of Systems Architecture: the EUROMICRO Journal - Special issue: Reconfigurable systems
The digital divide of computing
Proceedings of the 1st conference on Computing frontiers
Interprocedural Compiler Optimization for Partial Run-Time Reconfiguration
Journal of VLSI Signal Processing Systems
An application-centered design flow for self reconfigurable systems implementation
Proceedings of the 2009 Asia and South Pacific Design Automation Conference
IEICE - Transactions on Information and Systems
Reconfigurable Computing: The Theory and Practice of FPGA-Based Computation
Reconfigurable Computing: The Theory and Practice of FPGA-Based Computation
Reducing Memory Constraints in Modulo Scheduling Synthesis for FPGAs
ACM Transactions on Reconfigurable Technology and Systems (TRETS)
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The emergence of run-time reconfigurable architectures makes feasible the configure-execute paradigm. Compilation of behavioral descriptions (in, e.g., C, Java, etc.), apart from mapping the computational structures onto the available resources on the device, must split the program in temporal sections if it needs more resources than physically available. In addition, since the execution of the computational structures in a configuration needs at least two stages (i.e., configuring and computing), it is important to split the program such that the reconfiguration overheads are minimized, taking advantage of the overlapping of the execution stages on different configurations. This paper presents mapping techniques to cope with those features. The techniques are being researched in the context of a C compiler for the eXtreme Processing Platform (XPP). Temporal partitioning is applied to furnish a set of configurations that reduces the reconfiguration overhead and thus may lead to performance gains. We also show that when applications include a sequence of loops, the use of several configurations may be more beneficial than the mapping of the entire application onto a single configuration. Preliminary results for a number of benchmarks strongly confirm the approach.