An integrated temporal partioning and partial reconfiguration technique for design latency improvement

  • Authors:
  • Satish Ganesan;Ranga Vemuri

  • Affiliations:
  • Department of ECECS, ML 0030, University of Cincinnati,Cincinnati, OH;Department of ECECS, ML 0030, University of Cincinnati, Cincinnati, OH

  • Venue:
  • DATE '00 Proceedings of the conference on Design, automation and test in Europe
  • Year:
  • 2000

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Abstract