Algorithmic skeletons: structured management of parallel computation
Algorithmic skeletons: structured management of parallel computation
Structured development of parallel programs
Structured development of parallel programs
DATE '00 Proceedings of the conference on Design, automation and test in Europe
FPGA '02 Proceedings of the 2002 ACM/SIGDA tenth international symposium on Field-programmable gate arrays
Reconfigurable computing: a survey of systems and software
ACM Computing Surveys (CSUR)
Dynamic hardware plugins in an FPGA with partial run-time reconfiguration
Proceedings of the 39th annual Design Automation Conference
A Virtual Hardware Operating System for the Xilinx XC6200
FPL '96 Proceedings of the 6th International Workshop on Field-Programmable Logic, Smart Applications, New Paradigms and Compilers
Patterns and skeletons for parallel and distributed computing
Patterns and skeletons for parallel and distributed computing
System-Level Modeling of Dynamically Reconfigurable Hardware with SystemC
IPDPS '03 Proceedings of the 17th International Symposium on Parallel and Distributed Processing
Operating Systems for Reconfigurable Embedded Platforms: Online Scheduling of Real-Time Tasks
IEEE Transactions on Computers
Design Patterns for Reconfigurable Computing
FCCM '04 Proceedings of the 12th Annual IEEE Symposium on Field-Programmable Custom Computing Machines
From application descriptions to hardware in seconds: a logic-based approach to bridging the gap
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
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Reconfigurable hardware such as FPGAs combines performance and flexibility, two inherent requirements of many modern electronic devices. Moreover, using reconfigurable devices, time to market can be reduced while simultaneously cutting the costs. However, the design of systems that beneficially explore the reconfiguration capabilities of modern FPGAs is cumbersome and little automated. In this work, a new approach is described that starts from a very high level of abstraction, so-called algorithmic skeletons, and exploits the additional information of this level of abstraction to beneficially execute on reconfigurable devices. Particularly, the approach focuses on dynamic run-time reconfiguration on partially reconfigurable FPGAs. As a first introduction to this approach, we consider stream parallelism paradigms including their composition.