Realization of wireless multimedia communication systems on reconfigurable platforms
Journal of Systems Architecture: the EUROMICRO Journal - Special issue: Reconfigurable systems
ReChannel: Describing and simulating reconfigurable hardware in systemC
ACM Transactions on Design Automation of Electronic Systems (TODAES)
Journal of Systems Architecture: the EUROMICRO Journal
ACM Transactions on Reconfigurable Technology and Systems (TRETS)
Algorithmic skeletons for the programming of reconfigurable systems
SEUS'07 Proceedings of the 5th IFIP WG 10.2 international conference on Software technologies for embedded and ubiquitous systems
Evaluation of runtime task mapping heuristics with rSesame: a case study
Proceedings of the Conference on Design, Automation and Test in Europe
OSSS+R: a framework for application level modelling and synthesis of reconfigurable systems
Proceedings of the Conference on Design, Automation and Test in Europe
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To cope with the increasing demand for higher computational power and flexibility, dynamically re-configurable blocks become an important part inside a system-on-chip. Several methods have been proposed to incorporate their reconfiguration aspects in to a design flow. They all lack either an interface to commercially available and industrially used tools or are restricted to a single vendor or technology environment. Therefore a methodology for modeling of dynamically re-configurable blocks at the system-level using SystemC 2.0 is presented. The high-level model is based on a multi-context representation of the different functionalities that will be mapped on the re-configurable block during different run-time periods. By specifying the estimated times of context-switching and active-running in the selected functionality modes, the methodology allows to do true design space exploration at the system-level, without the need to map the design first to an actual technology implementation.