System-Level Modelling and Implementation Technique for Run-Time Reconfigurable Systems
FCCM '02 Proceedings of the 10th Annual IEEE Symposium on Field-Programmable Custom Computing Machines
System-Level Modeling of Dynamically Reconfigurable Hardware with SystemC
IPDPS '03 Proceedings of the 17th International Symposium on Parallel and Distributed Processing
Proceedings of the 2003 international conference on Compilers, architecture and synthesis for embedded systems
The MOLEN Polymorphic Processor
IEEE Transactions on Computers
An Execution Environment for Reconfigurable Computing
FCCM '05 Proceedings of the 13th Annual IEEE Symposium on Field-Programmable Custom Computing Machines
SystemC-based Design Methodology for Reconfigurable System-on-Chip
DSD '05 Proceedings of the 8th Euromicro Conference on Digital System Design
A Systematic Approach to Exploring Embedded System Architectures at Multiple Abstraction Levels
IEEE Transactions on Computers
Run-time management of a MPSoC containing FPGA fabric tiles
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
ACM Transactions on Reconfigurable Technology and Systems (TRETS)
Dynamic coprocessor management for FPGA-enhanced compute platforms
CASES '08 Proceedings of the 2008 international conference on Compilers, architectures and synthesis for embedded systems
System-level runtime mapping exploration of reconfigurable architectures
IPDPS '09 Proceedings of the 2009 IEEE International Symposium on Parallel&Distributed Processing
Evaluation of runtime task mapping using the rSesame framework
International Journal of Reconfigurable Computing - Special issue on Selected Papers from the International Conference on Reconfigurable Computing and FPGAs (ReConFig'10)
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rSesame is a generic modeling and simulation framework which can explore and evaluate reconfigurable systems at the early design stages. The framework can be used to explore different HW/SW partitionings, task mappings and scheduling strategies at both design time and runtime. The framework strives for a high degree of flexibility, ease of use, fast performance and applicability. In this paper, we want to evaluate the framework's characteristics by showing that it can easily and quickly model, simulate and compare a wide range of runtime mapping heuristics from various domains. A case study with a Motion-JPEG (MJPEG) application demonstrates that the presented model can be efficiently used to model and simulate a wide variety of mapping heuristics as well as to perform runtime exploration of various non-functional design parameters such as execution time, number of reconfigurations, area usage, etc.