Configuration prefetch for single context reconfigurable coprocessors
FPGA '98 Proceedings of the 1998 ACM/SIGDA sixth international symposium on Field programmable gate arrays
Proceedings of the 6th international workshop on Hardware/software codesign
CORDS: hardware-software co-synthesis of reconfigurable real-time distributed embedded systems
Proceedings of the 1998 IEEE/ACM international conference on Computer-aided design
Temporal Partitioning and Scheduling Data Flow Graphs for Reconfigurable Computers
IEEE Transactions on Computers
Kernel scheduling in reconfigurable computing
DATE '99 Proceedings of the conference on Design, automation and test in Europe
Software environment for a multiprocessor DSP
Proceedings of the 36th annual ACM/IEEE Design Automation Conference
The design of a low energy FPGA
ISLPED '99 Proceedings of the 1999 international symposium on Low power electronics and design
Power estimation approach for SRAM-based FPGAs
FPGA '00 Proceedings of the 2000 ACM/SIGDA eighth international symposium on Field programmable gate arrays
Low-power task scheduling for multiple devices
CODES '00 Proceedings of the eighth international workshop on Hardware/software codesign
Power analysis of embedded operating systems
Proceedings of the 37th Annual Design Automation Conference
A survey of design techniques for system-level dynamic power management
IEEE Transactions on Very Large Scale Integration (VLSI) Systems - Special section on low-power electronics and design
A decade of reconfigurable computing: a visionary retrospective
Proceedings of the conference on Design, automation and test in Europe
A HW/SW partitioning algorithm for dynamically reconfigurable architectures
Proceedings of the conference on Design, automation and test in Europe
Hardware-software cosynthesis for run-time incrementally reconfigurable FPGAs
ASP-DAC '00 Proceedings of the 2000 Asia and South Pacific Design Automation Conference
Proceedings of the ninth international symposium on Hardware/software codesign
Run-time HW/SW codesign for discrete event systems using dynamically reconfigurable architectures
ISSS '00 Proceedings of the 13th international symposium on System synthesis
ISSS '00 Proceedings of the 13th international symposium on System synthesis
Dynamic power consumption in Virtex™-II FPGA family
FPGA '02 Proceedings of the 2002 ACM/SIGDA tenth international symposium on Field-programmable gate arrays
Proceedings of the 15th international symposium on System Synthesis
Energy aware task scheduling with task synchronization for embedded real time systems
CASES '02 Proceedings of the 2002 international conference on Compilers, architecture, and synthesis for embedded systems
Scheduling for Embedded Real-Time Systems
IEEE Design & Test
Hardware-Software Codesign for Dynamically Reconfigurable Architectures
FPL '99 Proceedings of the 9th International Workshop on Field-Programmable Logic and Applications
A Virtual Hardware Operating System for the Xilinx XC6200
FPL '96 Proceedings of the 6th International Workshop on Field-Programmable Logic, Smart Applications, New Paradigms and Compilers
HW/SW codesign techniques for dynamically reconfigurable architectures
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Dynamic run-time HW/SW scheduling techniques for reconfigurable architectures
Proceedings of the tenth international symposium on Hardware/software codesign
Automating Production of Run-Time Reconfigurable Designs
FCCM '98 Proceedings of the IEEE Symposium on FPGAs for Custom Computing Machines
Preemptive Multitasking on FPGAs
FCCM '00 Proceedings of the 2000 IEEE Symposium on Field-Programmable Custom Computing Machines
ASP-DAC '02 Proceedings of the 2002 Asia and South Pacific Design Automation Conference
A Comparison of Five Different Multiprocessor SoC Bus Architectures
DSD '01 Proceedings of the Euromicro Symposium on Digital Systems Design
Multitasking on reconfigurable architectures: microarchitecture support and dynamic scheduling
ACM Transactions on Embedded Computing Systems (TECS)
Energy efficient co-scheduling in dynamically reconfigurable systems
CODES+ISSS '07 Proceedings of the 5th IEEE/ACM international conference on Hardware/software codesign and system synthesis
ACM Transactions on Reconfigurable Technology and Systems (TRETS)
System-Level Design Space Exploration of Dynamic Reconfigurable Architectures
SAMOS '08 Proceedings of the 8th international workshop on Embedded Computer Systems: Architectures, Modeling, and Simulation
Hardware task scheduling and placement in operating systems for dynamically reconfigurable SoC
Journal of Embedded Computing - Selected papers of EUC 2005
Evaluation of runtime task mapping heuristics with rSesame: a case study
Proceedings of the Conference on Design, Automation and Test in Europe
System-level power-performance tradeoffs for reconfigurable computing
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Hardware task scheduling and placement in operating systems for dynamically reconfigurable soc
EUC'05 Proceedings of the 2005 international conference on Embedded and Ubiquitous Computing
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Dynamic scheduling for System-on-Chip (SoC) platforms has become an important field of research due to the emerging range of applications with dynamic behavior (e.g. MPEG-4). Dynamically reconfigurable architectures are an interesting solution for this type of applications.However, dynamic scheduling for run-time reconfigurable architectures with power-performance trade-offs has not been addressed in previous research efforts. In this paper, we address this open issue using a system-level approach. Within our approach, we have used clock-gating and frequency-scaling strategies for power consumption minimization, jointly with our proposed architecture and scheduling algorithms.Device reconfiguration is a high-power consumption process. Thus reducing the number of device reconfigurations not only helps to reduce the reconfiguration overhead penalty (minimizing the application execution time), but also helps to reduce the system-level power consumption. Thus, dynamic task scheduling and reconfiguration context scheduling become a critical issue for power-performance trade-offs in embedded systems design.