Power estimation approach for SRAM-based FPGAs

Authors:
Karlheinz Weiß;Carsten Oetker;Igor Katchan;Thorsten Steckstor;Wolfgang Rosenstiel
Affiliations:
Forschungszentrum Informatik (FZI), Embedded System Design Group, Haid-und-Neu-Straβe 10, D-76131 Karlsruhe and the University of Tübingen, Technical Computer Science, Sand 13, D-72076 T ...;Forschungszentrum Informatik (FZI), Embedded System Design Group, Haid-und-Neu-Straβe 10, D-76131 Karlsruhe and the University of Tübingen, Technical Computer Science, Sand 13, D-72076 T ...;Forschungszentrum Informatik (FZI), Embedded System Design Group, Haid-und-Neu-Straβe 10, D-76131 Karlsruhe and the University of Tübingen, Technical Computer Science, Sand 13, D-72076 T ...;Forschungszentrum Informatik (FZI), Embedded System Design Group, Haid-und-Neu-Straβe 10, D-76131 Karlsruhe and the University of Tübingen, Technical Computer Science, Sand 13, D-72076 T ...;Forschungszentrum Informatik (FZI), Embedded System Design Group, Haid-und-Neu-Straβe 10, D-76131 Karlsruhe and the University of Tübingen, Technical Computer Science, Sand 13, D-72076 T ...
Venue:
FPGA '00 Proceedings of the 2000 ACM/SIGDA eighth international symposium on Field programmable gate arrays
Year:
2000

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Abstract

This paper presents the power consumption estimation for the novel Virtex architecture. Due to the fact that the XC4000 and the Virtex core architecture are very similar, we used the basic approaches for the XC4000-FPGAs power consumption estimation and extended that method for the new Virtex family. We determined an appropriate technology-dependent power factor Kp to calculate the power consumption on Virtex-chips, and developed a special benchmark test design to conduct our investigations. Additionally, the derived formulas are evaluated on two typical industrial designs. Our own emulation environments called SPYDER-ASIC-X1 and SPYDER-VIRTEX-X2 were used, which are best suited for the emulation of hardware designs for embedded systems.