Power estimation approach for SRAM-based FPGAs
FPGA '00 Proceedings of the 2000 ACM/SIGDA eighth international symposium on Field programmable gate arrays
High-Level Power Analysis and Optimization
High-Level Power Analysis and Optimization
Custom Memory Management Methodology: Exploration of Memory Organisation for Embedded Multimedia System Design
IEEE Transactions on Parallel and Distributed Systems
Scheduling of Partitioned Regular Algorithms on Processor Arrays with Constrained Resources
ASAP '96 Proceedings of the IEEE International Conference on Application-Specific Systems, Architectures, and Processors
High-Level Synthesis of Nonprogrammable Hardware Accelerators
ASAP '00 Proceedings of the IEEE International Conference on Application-Specific Systems, Architectures, and Processors
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We propose a high-level analytical model for estimating the energy and/or power dissipation in VLSI processor (systolic) array implementations of loop programs, particularly for implementations on FPGA based CO-processors. We focus on the respective impact of the array design parameters on the overall off-chip i/o traffic and the number and sizes of the local memories in the array. The model is validated experimentally and shows good results (12.7% RMS error in the predictions).