Optimization of the background memory utilization by partitioning
ISSS '97 Proceedings of the 10th international symposium on System synthesis
Combined instruction and loop parallelism in array synthesis for FPGAs
Proceedings of the 14th international symposium on Systems synthesis
Energy/power estimation of regular processor arrays
Proceedings of the 15th international symposium on System Synthesis
Performance-Scalable Array Architectures for Modular Multiplication
Journal of VLSI Signal Processing Systems
Loop Tiling for Reconfigurable Accelerators
FPL '01 Proceedings of the 11th International Conference on Field-Programmable Logic and Applications
Scheduling in Co-Partitioned Array Architectures
ASAP '97 Proceedings of the IEEE International Conference on Application-Specific Systems, Architectures and Processors
Determination of the Processor Functionality in the Design of Processor Arrays
ASAP '97 Proceedings of the IEEE International Conference on Application-Specific Systems, Architectures and Processors
Automatic Synthesis of FPGA Processor Arrays from Loop Algorithms
The Journal of Supercomputing
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A single integer linear programming model for optimally scheduling partitioned regular algorithms is presented. The herein presented methodology differs from existing methods in the following capabilities: 1) Not only constraints on the number of available processors and communication capabilities are taken into account, but also processor caches and constraints on the size of available memories are modeled and taken into account in the optimization model. 2) Different types of processors can be handled. 3) The size of the optimization model (number of integer variables) is independent of the size of the tiles to be executed. Hence, 4) the number of integer variables in the optimization model is greatly reduced such that problems of relevant size can be solved in practical execution time.