Regular interactive algorithms and their implementations on processor arrays
Regular interactive algorithms and their implementations on processor arrays
Theory of linear and integer programming
Theory of linear and integer programming
Resource constrained scheduling of uniform algorithms
Journal of VLSI Signal Processing Systems
The Organization of Computations for Uniform Recurrence Equations
Journal of the ACM (JACM)
Constructive Methods for Scheduling Uniform Loop Nests
IEEE Transactions on Parallel and Distributed Systems
Scheduling of Partitioned Regular Algorithms on Processor Arrays with Constrained Resources
ASAP '96 Proceedings of the IEEE International Conference on Application-Specific Systems, Architectures, and Processors
Automatic synthesis of systolic arrays from uniform recurrent equations
ISCA '84 Proceedings of the 11th annual international symposium on Computer architecture
Efficient exploration of affine space-time transformations for optimal systolic array synthesis
Efficient exploration of affine space-time transformations for optimal systolic array synthesis
Design of Processor Arrays for Reconfigurable Architectures
The Journal of Supercomputing
Localization of Data Transfer in Processor Arrays
Euro-Par '99 Proceedings of the 5th International Euro-Par Conference on Parallel Processing
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In this paper the inclusion of hardware constraints into the design of massively parallel processor arrays is considered. We propose an algorithm which determines an optimal scheduling function as well as the selection of components which have to be implemented in one processor of a processor array. The arising optimization problem is formulated as an integer linear program which also takes the necessary chip area of a hardware implementation into consideration. Thereby we assume that an allocation function is given and that a partitioning of the processor array is required to match a limited chip area in silicon.