Regular interactive algorithms and their implementations on processor arrays
Regular interactive algorithms and their implementations on processor arrays
Theory of linear and integer programming
Theory of linear and integer programming
VLSI array processors
Resource constrained scheduling of uniform algorithms
Journal of VLSI Signal Processing Systems
Resource-constrained scheduling of partitioned algorithms on processor arrays
Integration, the VLSI Journal
The Organization of Computations for Uniform Recurrence Equations
Journal of the ACM (JACM)
Mapping Nested Loop Algorithms into Multidimensional Systolic Arrays
IEEE Transactions on Parallel and Distributed Systems
Constructive Methods for Scheduling Uniform Loop Nests
IEEE Transactions on Parallel and Distributed Systems
Design of Processor Arrays for Real-Time Applications
Euro-Par '98 Proceedings of the 4th International Euro-Par Conference on Parallel Processing
Determination of the Processor Functionality in the Design of Processor Arrays
ASAP '97 Proceedings of the IEEE International Conference on Application-Specific Systems, Architectures and Processors
Efficient realization of data dependencies in algorithm partitioning under resource constraints
Euro-Par'06 Proceedings of the 12th international conference on Parallel Processing
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In this paper we present an approach to localize the data transfer in processor arrays. Our aim is to select channels between processors of the processor array performing the data transfers. Channels can be varying with respect to the bandwidth and to the communication delay and can be bidirectional. Our objective is to minimize the implementation cost of the channels while satisfying the data dependencies. The presented approach also applies to the problem of localizing data dependencies for a given interconnection topology. The formulation of our method as an integer linear program allows its use for automatic parallelization.