Resource constrained scheduling of uniform algorithms
Journal of VLSI Signal Processing Systems
Resource-constrained scheduling of partitioned algorithms on processor arrays
Integration, the VLSI Journal
The Organization of Computations for Uniform Recurrence Equations
Journal of the ACM (JACM)
Combined instruction and loop parallelism in array synthesis for FPGAs
Proceedings of the 14th international symposium on Systems synthesis
Fine-Grain Scheduling under Resource Constraints
LCPC '94 Proceedings of the 7th International Workshop on Languages and Compilers for Parallel Computing
Localization of Data Transfer in Processor Arrays
Euro-Par '99 Proceedings of the 5th International Euro-Par Conference on Parallel Processing
Algorithm Partitioning including Optimized Data-Reuse for Processor Arrays
PARELEC '04 Proceedings of the international conference on Parallel Computing in Electrical Engineering
Optimized Data-Reuse in Processor Arrays
ASAP '04 Proceedings of the Application-Specific Systems, Architectures and Processors, 15th IEEE International Conference
picoArray Technology: The Tool's Story
Proceedings of the conference on Design, Automation and Test in Europe - Volume 3
Minimum Cost for Channels and Registers in Processor Arrays by Avoiding Redundancy
ASAP '06 Proceedings of the IEEE 17th International Conference on Application-specific Systems, Architectures and Processors
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Mapping algorithms to parallel architectures efficiently is very important for a cost-effective design of many modern technical products. In this paper, we present a solution to the problem of efficiently realizing uniform data dependencies on processor arrays. In contrary to existing approaches, we formulate an optimization problem to consider the cost of both: channels and registers. Further, a solution to the optimization problem assigns which channels shall be implemented and it specifies the control for the realization of the uniform data dependencies. We illustrate our method on the edge detection algorithm.