Automatic Synthesis of FPGA Processor Arrays from Loop Algorithms

Authors:
Marcus Bednara;Jürgen Teich
Affiliations:
Computer Engineering Laboratory, University of Paderborn, Germany bednara@date.upb.de;Computer Engineering Laboratory, University of Paderborn, Germany teich@date.upb.de
Venue:
The Journal of Supercomputing
Year:
2003

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Abstract

We consider the problem of automatic mapping of computation-intensive loop nests onto FPGA hardware. The regular cell array structure of these chips reflects the parallelism in regular loop-like computations. Furthermore, the flexibility of FPGAs allows the cost-effective implementation of reconfigurable high performance processor arrays. So far, there exists no continuous design flow that allows automated generation of FPGA configuration data from a loop nest specified in a high level language. Here, we present a methodology for automatic generation of synthesizable VHDL code specifying a processor array and optimized for FPGA implementation.