In-place power optimization for LUT-based FPGAs
DAC '98 Proceedings of the 35th annual Design Automation Conference
A re-engineering approach to low power FPGA design using SPFD
DAC '98 Proceedings of the 35th annual Design Automation Conference
Introduction to data compression
Introduction to data compression
Power estimation approach for SRAM-based FPGAs
FPGA '00 Proceedings of the 2000 ACM/SIGDA eighth international symposium on Field programmable gate arrays
A n-Bit Reconfigurable Scalar Quantiser
FPL '01 Proceedings of the 11th International Conference on Field-Programmable Logic and Applications
Pipelining Considerations for an FPGA Case
DSD '01 Proceedings of the Euromicro Symposium on Digital Systems Design
A power-efficient processor core for reactive embedded applications
ACSAC'05 Proceedings of the 10th Asia-Pacific conference on Advances in Computer Systems Architecture
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This paper presents the evaluation in power consumption of a clocking technique for pipelined designs. The technique shows a dynamic power consumption saving of around 30% over a conventional global clocking mechanism. The results were obtained from a series of experiments of a systolic circuit implemented in Virtex-II devices. The conversion from a global-clocked pipelined design to the proposed technique is straightforward, preserving the original datapath design. The savings can be used immediately either as a power reduction benefit or to increase the frequency of operation of a design for the same power consumption.