Re-mapping for low power under tight timing constraints
ISLPED '97 Proceedings of the 1997 international symposium on Low power electronics and design
Low power FPGA design—a re-engineering approach
DAC '97 Proceedings of the 34th annual Design Automation Conference
Power optimization for FPGA look-up tables
Proceedings of the 1997 international symposium on Physical design
Rectification method for lookup-table type FPGA's
ICCAD '92 Proceedings of the 1992 IEEE/ACM international conference on Computer-aided design
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FPL '94 Proceedings of the 4th International Workshop on Field-Programmable Logic and Applications: Field-Programmable Logic, Architectures, Synthesis and Applications
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EDTC '96 Proceedings of the 1996 European conference on Design and Test
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IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Power and delay reduction via simultaneous logic and placement optimization in FPGAs
DATE '00 Proceedings of the conference on Design, automation and test in Europe
Power minization in LUT-based FPGA technology mapping
Proceedings of the 2001 Asia and South Pacific Design Automation Conference
A Clocking Technique with Power Savings in Virtex-Based Pipelined Designs
FPL '02 Proceedings of the Reconfigurable Computing Is Going Mainstream, 12th International Conference on Field-Programmable Logic and Applications
Low Power Technology Mapping for LUT based FPGA "A Genetic Algorithm Approach"
VLSID '03 Proceedings of the 16th International Conference on VLSI Design
Sa based power efficient FPGA LUT mapping
Proceedings of the 15th annual conference companion on Genetic and evolutionary computation
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This paper presents a new technique to perform power-oriented re-configuration of a system implemented using LUT FPGAs. The main features of our approach are: Accurate exploitation of degrees of freedom, concurrent optimization of multiple LUTs based on Boolean relations, and in-place re-programming without re-routing. Our tool optimizes the combinational component of the CLBs after layout, and does not require any re-wiring. Hence, delay and CLB usage are left unchanged, while power is minimized. As the algorithm operates locally on the various LUT clusters, it best performs on large examples as demonstrated by our experimental results: An average power reduction of 20.6% has been obtained on standard benchmarks.