FPGA Technology Mapping for Power Minimization

Combinational logic synthesis for LUT based field programmable gate arrays

ACM Transactions on Design Automation of Electronic Systems (TODAES)

Low power FPGA design—a re-engineering approach

DAC '97 Proceedings of the 34th annual Design Automation Conference

Power optimization for FPGA look-up tables

Proceedings of the 1997 international symposium on Physical design

In-place power optimization for LUT-based FPGAs

DAC '98 Proceedings of the 35th annual Design Automation Conference

Power minization in LUT-based FPGA technology mapping

Proceedings of the 2001 Asia and South Pacific Design Automation Conference

Switching activity analysis and pre-layout activity prediction for FPGAs

Proceedings of the 2003 international workshop on System-level interconnect prediction

Power minimization algorithms for LUT-based FPGA technology mapping

ACM Transactions on Design Automation of Electronic Systems (TODAES)

Low-power technology mapping for FPGA architectures with dual supply voltages

FPGA '04 Proceedings of the 2004 ACM/SIGDA 12th international symposium on Field programmable gate arrays

Interconnect capacitance estimation for FPGAs

Proceedings of the 2004 Asia and South Pacific Design Automation Conference

Power estimation techniques for FPGAs

IEEE Transactions on Very Large Scale Integration (VLSI) Systems

Hermes: LUT FPGA technology mapping algorithm for area minimization with optimum depth

Proceedings of the 2004 IEEE/ACM International conference on Computer-aided design

DAOmap: a depth-optimal area optimization mapping algorithm for FPGA designs

Proceedings of the 2004 IEEE/ACM International conference on Computer-aided design

Efficient LUT-based FPGA technology mapping for power minimization

ASP-DAC '03 Proceedings of the 2003 Asia and South Pacific Design Automation Conference

Power-aware FPGA logic synthesis using binary decision diagrams

Proceedings of the 2007 ACM/SIGDA 15th international symposium on Field programmable gate arrays

GlitchMap: an FPGA technology mapper for low power considering glitches

Proceedings of the 44th annual Design Automation Conference

Using negative edge triggered ffs to reduce glitching power in FPGA circuits

Proceedings of the 44th annual Design Automation Conference

FPGA Design Automation: A Survey

Foundations and Trends in Electronic Design Automation

Reconfigurable Computing: The Theory and Practice of FPGA-Based Computation

Reconfigurable Computing: The Theory and Practice of FPGA-Based Computation

Power-aware, depth-optimum and area minimization mapping of K-LUT based FPGA circuits

WSEAS Transactions on Computers

Technology mapping and clustering for FPGA architectures with dual supply voltages

IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems

Reducing the pressure on routing resources of FPGAs with generic logic chains

Proceedings of the 19th ACM/SIGDA international symposium on Field programmable gate arrays

Energy reduction by systematic run-time reconfigurable hardware deactivation

Transactions on High-Performance Embedded Architectures and Compilers IV

Sa based power efficient FPGA LUT mapping

Proceedings of the 15th annual conference companion on Genetic and evolutionary computation