An optimal on-line algorithm for metrical task system
Journal of the ACM (JACM)
A polylog(n)-competitive algorithm for metrical task systems
STOC '97 Proceedings of the twenty-ninth annual ACM symposium on Theory of computing
Configuration prefetch for single context reconfigurable coprocessors
FPGA '98 Proceedings of the 1998 ACM/SIGDA sixth international symposium on Field programmable gate arrays
Low-power task scheduling for multiple devices
CODES '00 Proceedings of the eighth international workshop on Hardware/software codesign
On-line Learning and the Metrical Task System Problem
Machine Learning
Evaluation of the streams-C C-to-FPGA compiler: an applications perspective
FPGA '01 Proceedings of the 2001 ACM/SIGDA ninth international symposium on Field programmable gate arrays
Dynamic hardware plugins in an FPGA with partial run-time reconfiguration
Proceedings of the 39th annual Design Automation Conference
Configuration relocation and defragmentation for run-time reconfigurable computing
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Scheduling for Embedded Real-Time Systems
IEEE Design & Test
Average-Case Competitive Analyses for Ski-Rental Problems
ISAAC '02 Proceedings of the 13th International Symposium on Algorithms and Computation
Dynamic run-time HW/SW scheduling techniques for reconfigurable architectures
Proceedings of the tenth international symposium on Hardware/software codesign
Performance of Remote FPGA-Based Coprocessors for Image-Processing Applications
DSD '02 Proceedings of the Euromicro Symposium on Digital Systems Design
The RAW benchmark suite: computation structures for general purpose computing
FCCM '97 Proceedings of the 5th IEEE Symposium on FPGA-Based Custom Computing Machines
Garp: a MIPS processor with a reconfigurable coprocessor
FCCM '97 Proceedings of the 5th IEEE Symposium on FPGA-Based Custom Computing Machines
The chimaera reconfigurable functional unit
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Minimization of the reconfiguration latency for the mapping of applications on FPGA-based systems
CODES+ISSS '09 Proceedings of the 7th IEEE/ACM international conference on Hardware/software codesign and system synthesis
Transmuting coprocessors: dynamic loading of FPGA coprocessors
Proceedings of the 46th Annual Design Automation Conference
Online SystemC emulation acceleration
Proceedings of the 47th Design Automation Conference
A single layer architecture to FPGA implementation of BP artificial neural network
CAR'10 Proceedings of the 2nd international Asia conference on Informatics in control, automation and robotics - Volume 2
Dynamic acceleration management for SystemC emulation
ACM SIGBED Review - Special Issue on the 2nd International Workshop on Adaptive and Reconfigurable Embedded Systems (APRES'09)
Evaluation of runtime task mapping heuristics with rSesame: a case study
Proceedings of the Conference on Design, Automation and Test in Europe
CODES+ISSS '11 Proceedings of the seventh IEEE/ACM/IFIP international conference on Hardware/software codesign and system synthesis
Evaluation of runtime task mapping using the rSesame framework
International Journal of Reconfigurable Computing - Special issue on Selected Papers from the International Conference on Reconfigurable Computing and FPGAs (ReConFig'10)
A self-adaptive heterogeneous multi-core architecture for embedded real-time video object tracking
Journal of Real-Time Image Processing
Energy-aware design of secure multi-mode real-time embedded systems with FPGA co-processors
Proceedings of the 21st International conference on Real-Time Networks and Systems
Optimization of interconnects between accelerators and shared memories in dark silicon
Proceedings of the International Conference on Computer-Aided Design
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Various commercial programmable compute platforms have their processor architecture enhanced with field-programmable gate arrays (FPGAs). In a common usage scenario, an application loads custom processors into the FPGA to speed up application execution compared to processor-only execution. Transient applications, changing application workloads, and limited FPGA capacity have led to a new problem of operating-system-controlled dynamic management of the loading of coprocessors into the FPGAs for best overall performance or energy. We define the Dynamic Coprocessor Management problem and provide a mapping to an online optimization problem known as Metrical Task Systems. We introduce a robust heuristic, called the fading cumulative benefit (FCBenefit) heuristic, that outperforms other heuristics, including a previously developed one for MTS. For two distinct application sets, we generate numerous workloads and show that the FCBenefit heuristic provides best results across all considered workloads. In our simulations, the heuristic's results were within 9% of the offline optimal for performance, and within 3% for energy. The heuristic may be applicable to a wide variety of dynamic architecture management problems.