Fundamentals of queueing theory (2nd ed.).
Fundamentals of queueing theory (2nd ed.).
Dynamic reconfiguration of FPGAs
Selected papers from the Oxford 1993 international workshop on field programmable logic and applications on More FPGAs
Scheduling designs into a time-multiplexed FPGA
FPGA '98 Proceedings of the 1998 ACM/SIGDA sixth international symposium on Field programmable gate arrays
PipeRench: a co/processor for streaming multimedia acceleration
ISCA '99 Proceedings of the 26th annual international symposium on Computer architecture
A low power unified cache architecture providing power and performance flexibility (poster session)
ISLPED '00 Proceedings of the 2000 international symposium on Low power electronics and design
Dynamic hardware plugins in an FPGA with partial run-time reconfiguration
Proceedings of the 39th annual Design Automation Conference
HW/SW codesign techniques for dynamically reconfigurable architectures
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Fast Online Task Placement on FPGAs: Free Space Partitioning and 2D-Hashing
IPDPS '03 Proceedings of the 17th International Symposium on Parallel and Distributed Processing
Run-time instruction set selection in a transmutable embedded processor
Proceedings of the 45th annual Design Automation Conference
Dynamic coprocessor management for FPGA-enhanced compute platforms
CASES '08 Proceedings of the 2008 international conference on Compilers, architectures and synthesis for embedded systems
Online SystemC emulation acceleration
Proceedings of the 47th Design Automation Conference
Dynamic acceleration management for SystemC emulation
ACM SIGBED Review - Special Issue on the 2nd International Workshop on Adaptive and Reconfigurable Embedded Systems (APRES'09)
Dynamic configuration prefetching based on piecewise linear prediction
Proceedings of the Conference on Design, Automation and Test in Europe
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Field-programmable gates arrays (FPGAs) are increasingly used in general-purpose computing platforms to augment microprocessors, enabling runtime loading of coprocessors customized to speed up some applications. Such transmuting coprocessors create new dynamic management problems involving decisions as to when to load a coprocessor, where to place the coprocessor in the FPGA, or which resident coprocessor to replace. We define a transmuting coprocessor problem based on Intel's FSB-FPGA architecture, with attention on communication and memory contention. We develop an online algorithm to manage coprocessor loading, the AG algorithm, which uses aggregated gains to guide coprocessor load, placement, replacement, and wait decisions. Experiments using embedded system applications, for random, biased, and periodic input application sequences, a range of reconfiguration times, and different FPGA types with different numbers of partial reconfigurable regions, demonstrate that the AG algorithm is robust across a variety of situations. The AG algorithm results are within 15% of an unlimited-size FPGA on average, exhibit a small standard deviation, and show a 1.4x speedup versus a static coprocessor loading approach and a 3x speedup over execution on a microprocessor-only solution.