Accelerating Run-Time Reconfiguration on FCCMs

Authors:
J-P Heron;R. F. Woods
Affiliations:
-;-
Venue:
FCCM '99 Proceedings of the Seventh Annual IEEE Symposium on Field-Programmable Custom Computing Machines
Year:
1999

Citing 4
Cited 2

A dynamic reconfiguration run-time system

FCCM '97 Proceedings of the 5th IEEE Symposium on FPGA-Based Custom Computing Machines
Automating Production of Run-Time Reconfigurable Designs

FCCM '98 Proceedings of the IEEE Symposium on FPGAs for Custom Computing Machines
Configuration Compression for the Xilinx XC6200 FPGA

FCCM '98 Proceedings of the IEEE Symposium on FPGAs for Custom Computing Machines
Design methodologies for partially reconfigured systems

FCCM '95 Proceedings of the IEEE Symposium on FPGA's for Custom Computing Machines

An integrated temporal partioning and partial reconfiguration technique for design latency improvement

DATE '00 Proceedings of the conference on Design, automation and test in Europe
Modeling and optimizing run-time reconfiguration using evolutionary computation

ACM Transactions on Embedded Computing Systems (TECS)

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Abstract

The paper describes the implementation of the arithmetic operations of multiplication, division and square root on a Xilinx XC6200 FPGA. By using a design approach to enhance similarities across circuits, partial reconfiguration has been used to allow reductions in reconfiguration times of up to 75% on trials using the VCC HOTWorks board.