Learning internal representations by error propagation
Parallel distributed processing: explorations in the microstructure of cognition, vol. 1
SPAA '92 Proceedings of the fourth annual ACM symposium on Parallel algorithms and architectures
Programmable active memories: a performance assessment
Proceedings of the 1993 symposium on Research on integrated systems
A field-programmable gate array for systolic computing
Proceedings of the 1993 symposium on Research on integrated systems
Applications of reconfigurable logic
Selected papers from the Oxford 1993 international workshop on field programmable logic and applications on More FPGAs
An FPGA-based hardware accelerator for image processing
Selected papers from the Oxford 1993 international workshop on field programmable logic and applications on More FPGAs
Artificial Neural Network Implementation on a Fine-Grained FPGA
FPL '94 Proceedings of the 4th International Workshop on Field-Programmable Logic and Applications: Field-Programmable Logic, Architectures, Synthesis and Applications
Plasma: an FPGA for million gate systems
Proceedings of the 1996 ACM fourth international symposium on Field-programmable gate arrays
Sequencing run-time reconfigured hardware with software
Proceedings of the 1996 ACM fourth international symposium on Field-programmable gate arrays
Improving functional density through run-time constant propagation
FPGA '97 Proceedings of the 1997 ACM fifth international symposium on Field-programmable gate arrays
Configuration caching vs data caching for striped FPGAs
FPGA '99 Proceedings of the 1999 ACM/SIGDA seventh international symposium on Field programmable gate arrays
Partitioning Sequential Circuits on Dynamically Reconfigurable FPGAs
IEEE Transactions on Computers
Computer Aided Design of Fault-Tolerant Application Specific Programmable Processors
IEEE Transactions on Computers
Dynamic hardware plugins in an FPGA with partial run-time reconfiguration
Proceedings of the 39th annual Design Automation Conference
Development of a Run-Time Reconfiguration System with Low Reconfiguration Overhead
Journal of VLSI Signal Processing Systems
Run-time performance optimization of an FPGA-based deduction engine for SAT solvers
ACM Transactions on Design Automation of Electronic Systems (TODAES)
Continuous and high coverage self-testing of dynamically re-configurable systems
Parallel Computing - Parallel computing in image and video processing
Implementing Kak Neural Networks on a Reconfigurable Computing Platform
FPL '00 Proceedings of the The Roadmap to Reconfigurable Computing, 10th International Workshop on Field-Programmable Logic and Applications
Using PARBIT to Implement Partial Run-Time Reconfigurable Systems
FPL '02 Proceedings of the Reconfigurable Computing Is Going Mainstream, 12th International Conference on Field-Programmable Logic and Applications
Accelerating Run-Time Reconfiguration on FCCMs
FCCM '99 Proceedings of the Seventh Annual IEEE Symposium on Field-Programmable Custom Computing Machines
Macro-instruction generation for dynamic logic caching
RSP '97 Proceedings of the 8th International Workshop on Rapid System Prototyping (RSP '97) Shortening the Path from Specification to Prototype
VLSID '97 Proceedings of the Tenth International Conference on VLSI Design: VLSI in Multimedia Applications
A Fast Macro Based Compilation Methodology for Partially Reconfigurable FPGA Designs
VLSID '03 Proceedings of the 16th International Conference on VLSI Design
An adaptive cryptographic engine for internet protocol security architectures
ACM Transactions on Design Automation of Electronic Systems (TODAES)
Run-Time Reconfigurable Systems for Digital Signal Processing Applications: A Survey
Journal of VLSI Signal Processing Systems
Run-time reconfigurable systems for digital signal processing applications: a survey
Journal of VLSI Signal Processing Systems
An efficient list scheduling algorithm for time placement problem
Computers and Electrical Engineering
Performance bounds of partial run-time reconfiguration in high-performance reconfigurable computing
HPRCTA '07 Proceedings of the 1st international workshop on High-performance reconfigurable computing technology and applications: held in conjunction with SC07
Exploiting Partial Runtime Reconfiguration for High-Performance Reconfigurable Computing
ACM Transactions on Reconfigurable Technology and Systems (TRETS)
Reconfigurable Computing: The Theory and Practice of FPGA-Based Computation
Reconfigurable Computing: The Theory and Practice of FPGA-Based Computation
Evolvable block-based neural network design for applications in dynamic environments
VLSI Design - Special issue on selected papers from the midwest symposium on circuits and systems
A dynamic hardware generation mechanism based on partial evaluation
DCC'96 Proceedings of the 3rd international conference on Designing Correct Circuits
ReShape: Towards a High-Level Approach to Design and Operation of Modular Reconfigurable Systems
ACM Transactions on Reconfigurable Technology and Systems (TRETS)
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Abstract: Run time reconfiguration (RTR) as an implementation approach that divides an application into a series of sequentially executed stages with each stage implemented as a separate circuit module. Partial RTR extends this approach by partitioning these stages and designing their circuit modules such that they exhibit a high degree of functional and physical commonality. Transitioning between configurations can then be accomplished by updating only the differences between configurations. This reduces the amount of time that an RTR application spends configuring and significantly enhances overall performance. The paper presents the design methodology for partial RTR in the context of RRANN2, a partial RTR artificial neural network.