Partitioning sequential circuits on dynamically reconfiguable FPGAs
FPGA '98 Proceedings of the 1998 ACM/SIGDA sixth international symposium on Field programmable gate arrays
Network flow based circuit partitioning for time-multiplexed FPGAs
Proceedings of the 1998 IEEE/ACM international conference on Computer-aided design
Proceedings of the 36th annual ACM/IEEE Design Automation Conference
Hardware-Software Cosynthesis for Digital Systems
IEEE Design & Test
Fast Template Placement for Reconfigurable Computing Systems
IEEE Design & Test
Proceedings of the 11 IPPS/SPDP'99 Workshops Held in Conjunction with the 13th International Parallel Processing Symposium and 10th Symposium on Parallel and Distributed Processing
An Enhanced Static-List Scheduling Algorithm for Temporal Partitioning onto RPUs
VLSI '99 Proceedings of the IFIP TC10/WG10.5 Tenth International Conference on Very Large Scale Integration: Systems on a Chip
Fast Online Task Placement on FPGAs: Free Space Partitioning and 2D-Hashing
IPDPS '03 Proceedings of the 17th International Symposium on Parallel and Distributed Processing
Design methodologies for partially reconfigured systems
FCCM '95 Proceedings of the IEEE Symposium on FPGA's for Custom Computing Machines
Task scheduling for heterogeneous reconfigurable computers
SBCCI '04 Proceedings of the 17th symposium on Integrated circuits and system design
A multi-mode video-stream processor with cyclically reconfigurable architecture
Proceedings of the 5th conference on Computing frontiers
A Performance Model for Run-Time Reconfigurable Hardware Accelerator
APPT '09 Proceedings of the 8th International Symposium on Advanced Parallel Processing Technologies
Towards Energy Aware Scheduling for Precedence Constrained Parallel Tasks in a Cluster with DVFS
CCGRID '10 Proceedings of the 2010 10th IEEE/ACM International Conference on Cluster, Cloud and Grid Computing
Dynamic application model for scheduling with uncertainty on reconfigurable architectures
International Journal of Reconfigurable Computing - Special issue on selected papers from the international workshop on reconfigurable communication-centric systems on chips (ReCoSoC' 2010)
Combining temporal partitioning and temporal placement techniques for communication cost improvement
Advances in Engineering Software
Resource management of distributed virtual machines
International Journal of Ad Hoc and Ubiquitous Computing
DVFS-control techniques for dense linear algebra operations on multi-core processors
Computer Science - Research and Development
Energy-aware parallel task scheduling in a cluster
Future Generation Computer Systems
Temporal partitioning of data flow graphs for reconfigurable architectures
International Journal of Computational Science and Engineering
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The partially reconfigurable FPGAs allows an overlap between the execution and the reconfiguration of tasks. The partial approach can be used to fit a large application into the FPGA device by partitioning the application over time. The executions being partitioned over time and the configurations of tasks are done so that the imposed constraints are satisfied. The main aim of this work consists in answering the question when will a task be mapped in the FPGA? A time placement algorithm based on the list scheduling technique is developed to solve efficiently the above question. We have just used the list scheduling algorithm because of its fast run time. Compared to the run time of other algorithms used in this filed like the spectral and ILP algorithms, the list scheduling algorithm remains a good temporal placement candidate, especially, for a several nodes graph. Also, a part of this paper is devoted for the study and the implementation of DCT task graph. This graph is the most computationally intensive part of the Color Layout Descriptor algorithm of a low-level visual descriptor of MPEG 7. The studied case shows that the use of the partial approach is very efficient in terms of latency of the whole application than the full one.