Combinatorics for computer science
Combinatorics for computer science
Field-programmable gate arrays
Field-programmable gate arrays
DPGA utilization and application
Proceedings of the 1996 ACM fourth international symposium on Field-programmable gate arrays
Buffer minimization and time-multiplexed I/O on dynamically reconfigurable FPGAs
FPGA '97 Proceedings of the 1997 ACM fifth international symposium on Field-programmable gate arrays
Synthesis and Optimization of Digital Circuits
Synthesis and Optimization of Digital Circuits
FCCM '97 Proceedings of the 5th IEEE Symposium on FPGA-Based Custom Computing Machines
Performance-Oriented Fully Routable Dynamic Architecture for a Field
Performance-Oriented Fully Routable Dynamic Architecture for a Field
Reconfigurable architectures for general-purpose computing
Reconfigurable architectures for general-purpose computing
Network flow based circuit partitioning for time-multiplexed FPGAs
Proceedings of the 1998 IEEE/ACM international conference on Computer-aided design
Circuit partitioning for dynamically reconfigurable FPGAs
FPGA '99 Proceedings of the 1999 ACM/SIGDA seventh international symposium on Field programmable gate arrays
A clustering- and probability-based approach for time-multiplexed FPGA partitioning
ICCAD '99 Proceedings of the 1999 IEEE/ACM international conference on Computer-aided design
A graph theoretic optimal algorithm for schedule compression in time-multiplexed FPGA partitioning
ICCAD '99 Proceedings of the 1999 IEEE/ACM international conference on Computer-aided design
A memory coherence technique for online transient error recovery of FPGA configurations
FPGA '01 Proceedings of the 2001 ACM/SIGDA ninth international symposium on Field programmable gate arrays
Temporal logic replication for dynamically reconfigurable FPGA partitioning
Proceedings of the 2002 international symposium on Physical design
Reconfigurable computing: a survey of systems and software
ACM Computing Surveys (CSUR)
Automated design synthesis and partitioning for adaptive reconfigurable hardware
Hardware implementation of intelligent systems
Performance-driven placement for dynamically reconfigurable FPGAs
ACM Transactions on Design Automation of Electronic Systems (TODAES)
Implementation of Virtual Circuits by Means of the FIPSOC Devices
FPL '00 Proceedings of the The Roadmap to Reconfigurable Computing, 10th International Workshop on Field-Programmable Logic and Applications
Online hardware/software partitioning in networked embedded systems
Proceedings of the 2005 Asia and South Pacific Design Automation Conference
An efficient list scheduling algorithm for time placement problem
Computers and Electrical Engineering
ACM Transactions on Reconfigurable Technology and Systems (TRETS)
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A fundamental feature of Dynamically Reconfigurable FP-GAs (DRFPGAs) is that the logic and interconnect is time-multiplexed. Thus for a circuit to be implemented on a DRFPGA, it needs to be partitioned such that each subcircuit can be executed at a different time. In this paper, the partitioning of sequential circuits for execution on a DRF-PGA is studied. To determine how to correctly partition a sequential circuit, and what are the costs in doing so, we propose a new gate-level model that handles time-multiplexed computation. We also introduce an enchanced force directed scheduling (FDS) algorithm to partition sequential circuits that finds a correct partition with low logic and communication costs, under the assumption that maximum performance is desired. We use our algorithm to partition seven large ISC AS'89 sequential benchmark circuits. The experimental results show that the enhanced FDS reduces communication costs by 27.5% with only a 1.1% increase in the gate cost compared to traditional FDS.