Buffer minimization and time-multiplexed I/O on dynamically reconfigurable FPGAs
FPGA '97 Proceedings of the 1997 ACM fifth international symposium on Field-programmable gate arrays
Managing pipeline-reconfigurable FPGAs
FPGA '98 Proceedings of the 1998 ACM/SIGDA sixth international symposium on Field programmable gate arrays
Scheduling designs into a time-multiplexed FPGA
FPGA '98 Proceedings of the 1998 ACM/SIGDA sixth international symposium on Field programmable gate arrays
Partitioning sequential circuits on dynamically reconfiguable FPGAs
FPGA '98 Proceedings of the 1998 ACM/SIGDA sixth international symposium on Field programmable gate arrays
Network flow based circuit partitioning for time-multiplexed FPGAs
Proceedings of the 1998 IEEE/ACM international conference on Computer-aided design
HSRA: high-speed, hierarchical synchronous reconfigurable array
FPGA '99 Proceedings of the 1999 ACM/SIGDA seventh international symposium on Field programmable gate arrays
Circuit partitioning for dynamically reconfigurable FPGAs
FPGA '99 Proceedings of the 1999 ACM/SIGDA seventh international symposium on Field programmable gate arrays
Partitioning Sequential Circuits on Dynamically Reconfigurable FPGAs
IEEE Transactions on Computers
Temporal Partitioning and Scheduling Data Flow Graphs for Reconfigurable Computers
IEEE Transactions on Computers
A clustering- and probability-based approach for time-multiplexed FPGA partitioning
ICCAD '99 Proceedings of the 1999 IEEE/ACM international conference on Computer-aided design
A graph theoretic optimal algorithm for schedule compression in time-multiplexed FPGA partitioning
ICCAD '99 Proceedings of the 1999 IEEE/ACM international conference on Computer-aided design
Journal of VLSI Signal Processing Systems - Special issue on VLSI on custom computing technology
Performance-driven placement for dynamically reconfigurable FPGAs
ACM Transactions on Design Automation of Electronic Systems (TODAES)
High-Level Partitioning of Digital Systems Based on Dynamically Reconfigurable Devices
FPL '02 Proceedings of the Reconfigurable Computing Is Going Mainstream, 12th International Conference on Field-Programmable Logic and Applications
A clustering- and probability-based approach for time-multiplexed FPGA partitioning
Integration, the VLSI Journal
A minimum communication cost algorithm for dynamically reconfigurable computing system
CSS '07 Proceedings of the Fifth IASTED International Conference on Circuits, Signals and Systems
An improved architecture for optimizing partitioning cost of time-multiplexed FPGA
CSS '07 Proceedings of the Fifth IASTED International Conference on Circuits, Signals and Systems
ACM Transactions on Reconfigurable Technology and Systems (TRETS)
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In this report we present a new architecture for a Field Programmable Logic Device. The architecture is geared towards routing completion and predictable timing performance. The central principle of the new architecture is based on the concept of efficient use of silicon resources. It is performance-oriented, with predictable interconnect and logic delays, and has a guaranteed routability. Latency in the original circuit is exploited in such a manner as to make efficient reuse of interconnect resources. Specifically, the given circuit is topologically levelized and implemented in a folded-pipeline manner. The new architecture is CAD friendly, thereby eliminating the need for complex time-consuming place and route tools.